Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3622356	1			T63	41		T64	1942		T65	256
values[2]	731055	1			T63	39		T64	540		T65	566
values[3]	104766	1			T63	3		T64	2		T65	341
values[4]	56168	1			T65	180		T399	441		T746	1
values[5]	37842	1			T65	106		T399	367		T746	1
values[6]	28471	1			T65	96		T399	216		T746	1
values[7]	22951	1			T65	68		T399	167		T746	1
values[8]	19461	1			T65	43		T399	132		T746	1
values[9]	16774	1			T65	45		T399	71		T746	1
values[10]	15067	1			T65	24		T399	57		T746	1
values[11]	13724	1			T65	26		T399	45		T746	1
values[12]	13543	1			T65	15		T399	46		T746	1
values[13]	12625	1			T65	11		T399	45		T746	1
values[14]	12221	1			T65	6		T399	56		T746	1
values[15]	11578	1			T65	2		T399	52		T746	1
values[16]	10952	1			T65	5		T399	58		T746	1
values[17]	10319	1			T65	10		T399	57		T746	1
values[18]	10049	1			T65	11		T399	44		T746	1
values[19]	9823	1			T65	13		T399	33		T746	1
values[20]	9239	1			T65	7		T399	24		T746	1
values[21]	8807	1			T65	3		T399	9		T746	1
values[22]	8296	1			T65	6		T399	11		T746	1
values[23]	8180	1			T65	9		T399	7		T746	1
values[24]	8247	1			T65	9		T399	16		T746	1
values[25]	7959	1			T65	4		T399	7		T746	1
values[26]	7473	1			T65	5		T399	10		T746	1
values[27]	7030	1			T65	5		T399	8		T746	1
values[28]	6585	1			T65	5		T399	8		T746	1
values[29]	6296	1			T65	3		T399	7		T746	1
values[30]	6101	1			T65	5		T399	15		T746	1
values[31]	5608	1			T65	9		T399	9		T746	1
values[32]	5014	1			T65	11		T399	6		T746	1
values[33]	4691	1			T65	10		T399	7		T746	1
values[34]	4433	1			T65	14		T399	7		T746	1
values[35]	4297	1			T65	16		T399	7		T746	1
values[36]	4053	1			T65	17		T399	6		T746	1
values[37]	3930	1			T65	9		T399	13		T746	1
values[38]	3716	1			T65	10		T399	9		T746	1
values[39]	3548	1			T65	7		T399	5		T746	1
values[40]	3514	1			T65	6		T399	7		T746	1
values[41]	3394	1			T65	5		T399	6		T746	1
values[42]	3272	1			T65	4		T399	6		T746	1
values[43]	3196	1			T65	7		T399	7		T746	1
values[44]	3093	1			T65	6		T399	9		T746	1
values[45]	3100	1			T65	3		T399	4		T746	1
values[46]	3067	1			T65	8		T399	4		T746	1
values[47]	3099	1			T65	4		T399	10		T746	1
values[48]	3045	1			T65	2		T399	7		T746	1
values[49]	2946	1			T65	4		T399	11		T746	1
values[50]	2911	1			T65	5		T399	11		T746	1
values[51]	2803	1			T65	4		T399	6		T746	1
values[52]	2765	1			T65	1		T399	6		T746	1
values[53]	2695	1			T65	1		T399	6		T746	1
values[54]	2597	1			T65	1		T399	4		T746	1
values[55]	2557	1			T65	1		T399	4		T746	1
values[56]	2550	1			T65	2		T399	6		T746	1
values[57]	2522	1			T65	2		T399	11		T746	1
values[58]	2533	1			T65	2		T399	16		T746	1
values[59]	2488	1			T65	1		T399	6		T746	1
values[60]	2613	1			T65	3		T399	5		T746	1
values[61]	2866	1			T65	2		T399	7		T746	1
values[62]	4495	1			T65	4		T399	15		T746	1
values[63]	17449	1			T65	33		T399	62		T746	30
values[64]	229839	1			T65	66		T399	165		T746	176

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4676854	1			T63	111		T64	2063		T65	1638
values[2]	774628	1			T63	40		T64	549		T65	469
values[3]	78700	1			T63	16		T64	13		T65	92
values[4]	14433	1			T63	9		T64	2		T65	2
values[5]	5691	1			T63	3		T64	2		T399	4
values[6]	3382	1			T64	1		T399	6		T400	1
values[7]	2477	1			T399	9		T400	4		T379	4
values[8]	2182	1			T399	15		T400	1		T379	4
values[9]	2077	1			T399	11		T400	1		T379	4
values[10]	1864	1			T399	3		T400	4		T379	4
values[11]	1746	1			T399	5		T400	1		T379	4
values[12]	1518	1			T399	7		T400	2		T379	5
values[13]	1419	1			T399	9		T400	1		T379	4
values[14]	1323	1			T399	7		T400	3		T379	5
values[15]	1337	1			T399	6		T400	1		T379	4
values[16]	1287	1			T399	4		T400	1		T379	4
values[17]	1173	1			T399	4		T400	1		T379	4
values[18]	1074	1			T399	3		T400	4		T379	2
values[19]	987	1			T399	4		T400	3		T379	2
values[20]	968	1			T399	5		T400	6		T379	2
values[21]	962	1			T399	5		T400	5		T379	2
values[22]	973	1			T399	5		T400	1		T379	2
values[23]	829	1			T399	4		T400	2		T379	2
values[24]	786	1			T399	2		T400	1		T379	2
values[25]	786	1			T399	6		T400	2		T379	2
values[26]	786	1			T399	4		T400	1		T379	2
values[27]	744	1			T399	5		T400	1		T379	2
values[28]	828	1			T399	2		T400	1		T379	2
values[29]	756	1			T399	4		T400	1		T379	1
values[30]	685	1			T399	4		T400	1		T379	1
values[31]	630	1			T399	3		T400	5		T379	2
values[32]	589	1			T399	2		T400	1		T379	2
values[33]	582	1			T399	7		T400	1		T379	2
values[34]	627	1			T399	9		T400	3		T379	2
values[35]	544	1			T399	8		T400	2		T379	2
values[36]	510	1			T399	6		T400	1		T379	2
values[37]	500	1			T399	7		T400	1		T379	2
values[38]	480	1			T399	3		T400	1		T379	2
values[39]	507	1			T399	4		T400	1		T379	2
values[40]	513	1			T399	7		T400	1		T379	3
values[41]	470	1			T399	3		T400	1		T379	2
values[42]	463	1			T399	2		T400	1		T379	1
values[43]	506	1			T399	5		T400	3		T379	1
values[44]	524	1			T399	5		T400	1		T379	2
values[45]	524	1			T399	5		T400	2		T379	2
values[46]	491	1			T399	2		T400	1		T379	2
values[47]	501	1			T399	6		T400	1		T379	2
values[48]	467	1			T399	5		T400	1		T379	2
values[49]	470	1			T399	5		T400	4		T379	2
values[50]	429	1			T399	4		T400	1		T379	2
values[51]	400	1			T399	3		T400	2		T379	2
values[52]	417	1			T399	2		T400	1		T379	2
values[53]	438	1			T399	3		T400	2		T379	2
values[54]	435	1			T399	2		T400	5		T379	2
values[55]	422	1			T399	3		T400	2		T379	2
values[56]	367	1			T399	5		T400	1		T379	1
values[57]	342	1			T399	8		T400	1		T379	2
values[58]	343	1			T399	3		T400	2		T379	2
values[59]	332	1			T399	3		T400	1		T379	2
values[60]	332	1			T399	4		T400	1		T379	2
values[61]	420	1			T399	7		T400	2		T379	2
values[62]	765	1			T399	11		T400	1		T379	2
values[63]	3409	1			T399	49		T400	1		T379	3
values[64]	25109	1			T399	118		T400	152		T379	91

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	599720	1			T63	1		T64	17		T65	9
values[2]	2542722	1			T63	94		T64	1943		T65	170
values[3]	1132408	1			T63	39		T64	466		T65	551
values[4]	150169	1			T63	2		T64	2		T65	345
values[5]	77907	1			T65	192		T79	1		T113	1
values[6]	50339	1			T65	127		T79	1		T399	429
values[7]	36211	1			T65	69		T399	311		T746	1
values[8]	28327	1			T65	45		T399	178		T746	1
values[9]	23840	1			T65	32		T399	123		T746	1
values[10]	21131	1			T65	34		T399	113		T746	1
values[11]	19055	1			T65	19		T399	98		T746	1
values[12]	17368	1			T65	39		T399	88		T746	1
values[13]	15768	1			T65	43		T399	78		T746	1
values[14]	14624	1			T65	27		T399	50		T746	1
values[15]	13770	1			T65	8		T399	36		T746	1
values[16]	13386	1			T65	8		T399	25		T746	1
values[17]	12650	1			T65	8		T399	43		T746	1
values[18]	12106	1			T65	12		T399	61		T746	1
values[19]	11763	1			T65	8		T399	41		T746	1
values[20]	11284	1			T65	4		T399	16		T746	1
values[21]	10727	1			T65	4		T399	15		T746	1
values[22]	10217	1			T65	6		T399	13		T746	1
values[23]	9734	1			T65	14		T399	6		T746	1
values[24]	9009	1			T65	11		T399	8		T746	1
values[25]	8879	1			T65	6		T399	9		T746	1
values[26]	8670	1			T65	6		T399	8		T746	1
values[27]	8308	1			T65	6		T399	10		T746	1
values[28]	7706	1			T65	8		T399	10		T746	1
values[29]	7274	1			T65	6		T399	10		T746	1
values[30]	6690	1			T65	10		T399	15		T746	1
values[31]	6362	1			T65	11		T399	11		T746	1
values[32]	5819	1			T65	9		T399	6		T746	1
values[33]	5459	1			T65	6		T399	8		T746	1
values[34]	5057	1			T65	10		T399	5		T746	1
values[35]	4870	1			T65	22		T399	6		T746	1
values[36]	4521	1			T65	9		T399	11		T746	1
values[37]	4197	1			T65	2		T399	7		T746	1
values[38]	4031	1			T65	3		T399	7		T746	1
values[39]	3845	1			T65	3		T399	13		T746	1
values[40]	3678	1			T65	2		T399	5		T746	1
values[41]	3544	1			T65	6		T399	6		T746	1
values[42]	3478	1			T65	5		T399	4		T746	1
values[43]	3437	1			T65	4		T399	5		T746	1
values[44]	3374	1			T65	8		T399	14		T746	1
values[45]	3228	1			T65	12		T399	9		T746	1
values[46]	3246	1			T65	7		T399	5		T746	1
values[47]	3331	1			T65	10		T399	11		T746	1
values[48]	3133	1			T65	4		T399	11		T746	1
values[49]	3029	1			T65	4		T399	12		T746	1
values[50]	2985	1			T65	5		T399	7		T746	1
values[51]	2987	1			T65	6		T399	9		T746	1
values[52]	2966	1			T65	5		T399	13		T746	1
values[53]	3006	1			T65	15		T399	18		T746	1
values[54]	2920	1			T65	11		T399	17		T746	1
values[55]	2925	1			T65	2		T399	5		T746	1
values[56]	2738	1			T65	3		T399	3		T746	1
values[57]	2757	1			T65	1		T399	7		T746	1
values[58]	2710	1			T65	4		T399	4		T746	1
values[59]	2647	1			T65	2		T399	4		T746	1
values[60]	2741	1			T65	2		T399	4		T746	1
values[61]	2925	1			T65	3		T399	9		T746	1
values[62]	4275	1			T65	4		T399	43		T746	1
values[63]	19059	1			T65	2		T399	120		T746	1
values[64]	217270	1			T65	2		T399	196		T746	182