Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1905219	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

20617613

1

T1

4421

T2

5821

T3

19683

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14180010	1			T1	1370		T2	2531		T3	15523
values[0x0]	6945035	1			T1	3051		T2	3290		T3	4160
values[0x1]	1397787	1			T1	176		T2	456		T3	4255

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	636161	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21886671

1

T1

4597

T2

6277

T3

23938

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10110017	1			T1	2299		T2	3139		T3	11969
valid_sources[0x01]	10109329	1			T1	2298		T2	3138		T3	11969
valid_sources[0x02]	36166	1			T187	168		T181	75		T188	183
valid_sources[0x03]	37120	1			T196	5		T187	187		T181	46
valid_sources[0x04]	37118	1			T187	151		T181	87		T491	5
valid_sources[0x05]	36440	1			T187	175		T181	93		T188	180
valid_sources[0x06]	36575	1			T66	1		T187	174		T181	101
valid_sources[0x07]	39729	1			T66	1		T187	186		T181	68
valid_sources[0x08]	37547	1			T66	1		T187	162		T181	80
valid_sources[0x09]	36106	1			T187	178		T181	76		T188	175
valid_sources[0x0a]	37367	1			T187	185		T181	90		T188	167
valid_sources[0x0b]	36030	1			T187	149		T181	80		T188	156
valid_sources[0x0c]	37315	1			T187	194		T181	103		T188	167
valid_sources[0x0d]	37426	1			T187	154		T181	64		T491	1
valid_sources[0x0e]	36411	1			T66	1		T187	153		T181	107
valid_sources[0x0f]	38183	1			T66	1		T187	167		T181	68
valid_sources[0x10]	37227	1			T187	149		T181	86		T188	170
valid_sources[0x11]	37107	1			T187	169		T181	77		T491	1
valid_sources[0x12]	36776	1			T187	141		T181	69		T491	6
valid_sources[0x13]	37413	1			T187	184		T181	103		T491	8
valid_sources[0x14]	36707	1			T66	1		T187	164		T181	50
valid_sources[0x15]	37294	1			T66	1		T187	176		T181	93
valid_sources[0x16]	37457	1			T187	182		T181	56		T188	175
valid_sources[0x17]	36985	1			T187	188		T181	66		T188	176
valid_sources[0x18]	37152	1			T66	1		T187	192		T181	76
valid_sources[0x19]	36935	1			T187	151		T181	74		T188	183
valid_sources[0x1a]	37015	1			T66	2		T187	168		T181	102
valid_sources[0x1b]	36804	1			T187	178		T181	66		T188	163
valid_sources[0x1c]	36388	1			T66	2		T195	39		T196	12
valid_sources[0x1d]	36884	1			T66	1		T187	152		T181	79
valid_sources[0x1e]	37341	1			T66	1		T187	161		T181	102
valid_sources[0x1f]	36987	1			T66	1		T187	184		T181	56
valid_sources[0x20]	37414	1			T66	3		T187	156		T181	81

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13468532

1

T1

1370

T2

2531

T3

15523

values[0x0]

all_enables

biggest_size

6904842

1

T1

3051

T2

3290

T3

4160

values[0x1]

all_enables

biggest_size

244239

1

T66

21

T68

20

T69

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2726944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

430869

1

T63

8

T64

298

T65

278

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1071808	1			T63	25		T64	849		T65	740
values[0x0]	1017171	1			T63	28		T64	766		T65	714
values[0x1]	1068834	1			T63	30		T64	869		T65	711

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2112335	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1045478

1

T63

26

T64

786

T65

703

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50419	1			T63	4		T64	42		T65	33
valid_sources[0x01]	49977	1			T63	2		T64	18		T65	16
valid_sources[0x02]	49021	1			T63	1		T64	36		T65	57
valid_sources[0x03]	48664	1			T63	1		T64	45		T65	21
valid_sources[0x04]	48242	1			T64	46		T65	33		T70	12
valid_sources[0x05]	49475	1			T64	35		T65	30		T399	7
valid_sources[0x06]	48893	1			T63	1		T64	46		T65	31
valid_sources[0x07]	50177	1			T64	11		T65	32		T70	17
valid_sources[0x08]	50372	1			T63	2		T64	38		T65	24
valid_sources[0x09]	48522	1			T64	19		T65	44		T113	1
valid_sources[0x0a]	48432	1			T64	42		T65	32		T79	3
valid_sources[0x0b]	50845	1			T64	23		T65	37		T113	1
valid_sources[0x0c]	49745	1			T63	2		T64	42		T65	38
valid_sources[0x0d]	49313	1			T64	51		T65	41		T70	2
valid_sources[0x0e]	49365	1			T63	3		T64	47		T65	52
valid_sources[0x0f]	49120	1			T63	2		T64	50		T65	20
valid_sources[0x10]	48486	1			T63	2		T64	27		T65	29
valid_sources[0x11]	48734	1			T64	20		T65	26		T79	4
valid_sources[0x12]	49926	1			T64	29		T65	46		T79	2
valid_sources[0x13]	50363	1			T64	55		T65	37		T399	9
valid_sources[0x14]	48992	1			T63	2		T64	58		T65	33
valid_sources[0x15]	48780	1			T63	2		T64	52		T65	27
valid_sources[0x16]	49259	1			T63	2		T64	56		T65	37
valid_sources[0x17]	48359	1			T64	46		T65	38		T79	18
valid_sources[0x18]	50353	1			T63	2		T64	49		T65	43
valid_sources[0x19]	49818	1			T64	23		T65	39		T113	2
valid_sources[0x1a]	49243	1			T63	4		T64	42		T65	31
valid_sources[0x1b]	50283	1			T63	5		T64	31		T65	21
valid_sources[0x1c]	49106	1			T63	6		T64	34		T65	24
valid_sources[0x1d]	49369	1			T64	32		T65	27		T79	7
valid_sources[0x1e]	49324	1			T63	2		T64	4		T65	51
valid_sources[0x1f]	49560	1			T64	36		T65	31		T79	14
valid_sources[0x20]	49070	1			T63	2		T64	69		T65	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45285

1

T64

35

T65

22

T70

6

values[0x0]

all_enables

biggest_size

340395

1

T63

8

T64

228

T65

225

values[0x1]

all_enables

biggest_size

45189

1

T64

35

T65

31

T70

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2914524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

474147

1

T63

23

T64

348

T65

313

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1160026	1			T63	58		T64	905		T65	727
values[0x0]	1067407	1			T63	46		T64	821		T65	718
values[0x1]	1161238	1			T63	75		T64	904		T65	756

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2235520	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1153151

1

T63

61

T64

861

T65

761

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53041	1			T63	1		T64	45		T65	50
valid_sources[0x01]	53297	1			T63	1		T64	45		T65	60
valid_sources[0x02]	52860	1			T63	3		T64	47		T65	21
valid_sources[0x03]	52018	1			T63	3		T64	40		T65	37
valid_sources[0x04]	52234	1			T64	45		T65	23		T70	1
valid_sources[0x05]	52922	1			T63	4		T64	41		T65	23
valid_sources[0x06]	52981	1			T63	3		T64	43		T65	36
valid_sources[0x07]	53467	1			T63	1		T64	40		T65	14
valid_sources[0x08]	53386	1			T63	1		T64	44		T65	36
valid_sources[0x09]	52624	1			T63	6		T64	35		T65	50
valid_sources[0x0a]	52458	1			T63	7		T64	43		T65	35
valid_sources[0x0b]	54012	1			T63	3		T64	53		T65	43
valid_sources[0x0c]	51615	1			T64	41		T65	39		T79	29
valid_sources[0x0d]	52555	1			T63	3		T64	46		T65	40
valid_sources[0x0e]	52935	1			T63	5		T64	41		T65	28
valid_sources[0x0f]	53163	1			T63	5		T64	45		T65	40
valid_sources[0x10]	52192	1			T63	1		T64	42		T65	37
valid_sources[0x11]	51801	1			T63	2		T64	39		T65	33
valid_sources[0x12]	52883	1			T63	1		T64	43		T65	46
valid_sources[0x13]	53619	1			T64	39		T65	45		T79	16
valid_sources[0x14]	53743	1			T63	3		T64	25		T65	57
valid_sources[0x15]	52463	1			T63	6		T64	36		T65	34
valid_sources[0x16]	52375	1			T63	5		T64	38		T65	48
valid_sources[0x17]	52260	1			T63	3		T64	49		T65	28
valid_sources[0x18]	53747	1			T63	1		T64	38		T65	39
valid_sources[0x19]	52297	1			T63	1		T64	48		T65	35
valid_sources[0x1a]	53640	1			T63	2		T64	40		T65	27
valid_sources[0x1b]	52198	1			T63	2		T64	49		T65	30
valid_sources[0x1c]	52805	1			T63	5		T64	34		T65	29
valid_sources[0x1d]	52556	1			T63	3		T64	39		T65	37
valid_sources[0x1e]	52296	1			T63	1		T64	42		T65	39
valid_sources[0x1f]	52809	1			T63	3		T64	35		T65	24
valid_sources[0x20]	52599	1			T63	8		T64	38		T65	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49934

1

T64

43

T65

23

T70

1

values[0x0]

all_enables

biggest_size

374075

1

T63

21

T64

269

T65

260

values[0x1]

all_enables

biggest_size

50138

1

T63

2

T64

36

T65

30

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2747603	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

433658

1

T63

12

T64

331

T65

289

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1077264	1			T63	46		T64	771		T65	638
values[0x0]	1025555	1			T63	43		T64	812		T65	722
values[0x1]	1078442	1			T63	47		T64	845		T65	671

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2126515	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1054746

1

T63

42

T64

812

T65

708

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49899	1			T63	8		T64	27		T65	33
valid_sources[0x01]	50362	1			T64	34		T65	31		T70	3
valid_sources[0x02]	50452	1			T63	2		T64	85		T65	24
valid_sources[0x03]	49892	1			T64	27		T65	37		T70	2
valid_sources[0x04]	49213	1			T64	15		T65	44		T79	6
valid_sources[0x05]	49535	1			T64	61		T65	37		T70	5
valid_sources[0x06]	49446	1			T64	44		T65	33		T70	1
valid_sources[0x07]	49223	1			T65	35		T70	17		T79	9
valid_sources[0x08]	49773	1			T64	19		T65	27		T70	1
valid_sources[0x09]	50008	1			T63	9		T64	34		T65	26
valid_sources[0x0a]	49160	1			T64	24		T65	29		T70	5
valid_sources[0x0b]	50577	1			T63	2		T64	49		T65	34
valid_sources[0x0c]	49073	1			T63	3		T64	21		T65	28
valid_sources[0x0d]	49685	1			T64	19		T65	41		T70	1
valid_sources[0x0e]	49922	1			T64	55		T65	49		T70	7
valid_sources[0x0f]	49054	1			T64	20		T65	32		T70	4
valid_sources[0x10]	49624	1			T64	52		T65	40		T79	4
valid_sources[0x11]	48850	1			T64	29		T65	19		T70	2
valid_sources[0x12]	49969	1			T64	10		T65	33		T70	5
valid_sources[0x13]	50089	1			T63	1		T64	55		T65	35
valid_sources[0x14]	49552	1			T64	82		T65	32		T70	6
valid_sources[0x15]	49007	1			T64	78		T65	39		T70	3
valid_sources[0x16]	49833	1			T63	1		T64	37		T65	25
valid_sources[0x17]	50137	1			T64	41		T65	33		T70	1
valid_sources[0x18]	50143	1			T63	7		T64	12		T65	39
valid_sources[0x19]	49482	1			T63	19		T64	97		T65	32
valid_sources[0x1a]	50119	1			T63	1		T64	53		T65	29
valid_sources[0x1b]	50571	1			T63	1		T64	74		T65	33
valid_sources[0x1c]	49926	1			T64	25		T65	34		T70	3
valid_sources[0x1d]	50226	1			T64	7		T65	27		T79	11
valid_sources[0x1e]	49657	1			T64	22		T65	15		T70	10
valid_sources[0x1f]	49597	1			T63	22		T64	75		T65	30
valid_sources[0x20]	50290	1			T64	27		T65	30		T70	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45740

1

T64

33

T65

29

T70

4

values[0x0]

all_enables

biggest_size

342317

1

T63

10

T64

268

T65

230

values[0x1]

all_enables

biggest_size

45601

1

T63

2

T64

30

T65

30