Module Definition
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Module : hmac
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_hmac 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_hmac

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.61 90.68 93.15 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : hmac
TotalCoveredPercent
Totals 33 33 100.00
Total Bits 316 316 100.00
Total Bits 0->1 158 158 100.00
Total Bits 1->0 158 158 100.00

Ports 33 33 100.00
Port Bits 316 316 100.00
Port Bits 0->1 158 158 100.00
Port Bits 1->0 158 158 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T29,T30,T34 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T29,T30,T34 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T62,T339,T317 Yes T62,T339,T317 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T62,T339,T317 Yes T62,T339,T317 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T62,T339,T317 Yes T62,T339,T317 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T62,T339,T317 Yes T62,T339,T317 INPUT
tl_i.a_mask[3:0] Yes Yes T62,T339,T317 Yes T62,T339,T317 INPUT
tl_i.a_address[12:0] Yes Yes *T63,*T64,*T70 Yes T63,T64,T70 INPUT
tl_i.a_address[15:13] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T62,*T339,*T317 Yes T62,T339,T317 INPUT
tl_i.a_address[19:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T62,*T339,*T317 Yes T62,T339,T317 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T62,*T339,*T317 Yes T62,T339,T317 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T62,*T339,*T317 Yes T62,T339,T317 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T195,*T196,*T63 Yes T195,T196,T63 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T63,T64,T70 Yes T63,T64,T70 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T339,T317,T318 Yes T339,T317,T318 INPUT
tl_i.a_valid Yes Yes T62,T339,T317 Yes T62,T339,T317 INPUT
tl_o.a_ready Yes Yes T62,T339,T317 Yes T62,T339,T317 OUTPUT
tl_o.d_error Yes Yes T64,T70,T79 Yes T63,T64,T70 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T339,T317,T318 Yes T339,T317,T318 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T339,T317,T318 Yes T339,T317,T318 OUTPUT
tl_o.d_data[31:0] Yes Yes T62,T339,T317 Yes T339,T317,T318 OUTPUT
tl_o.d_sink Yes Yes T63,T64,T70 Yes T63,T64,T70 OUTPUT
tl_o.d_source[5:0] Yes Yes *T195,*T196,*T64 Yes T195,T196,T63 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T64,T70,T79 Yes T63,T64,T70 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T62,*T339,*T317 Yes T339,T317,T318 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T62,T339,T317 Yes T62,T339,T317 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T62,T131,T83 Yes T62,T131,T83 INPUT
alert_rx_i[0].ping_n Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
alert_rx_i[0].ping_p Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T62,T131,T83 Yes T62,T131,T83 OUTPUT
intr_hmac_done_o Yes Yes T317,T318,T120 Yes T317,T318,T120 OUTPUT
intr_fifo_empty_o Yes Yes T288,T289,T298 Yes T288,T289,T298 OUTPUT
intr_hmac_err_o Yes Yes T288,T289,T298 Yes T288,T289,T298 OUTPUT
idle_o[3:0] Yes Yes T1,T2,T3 Yes T29,T30,T34 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%