Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295593825	33965155	0	0
DepthKnown_A	295593825	295510316	0	0
RvalidKnown_A	295593825	295510316	0	0
WreadyKnown_A	295593825	295510316	0	0
gen_passthru_fifo.paramCheckPass	840	840	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	33965155	0	0
T1	138066	17262	0	0
T2	93452	9897	0	0
T3	227035	23423	0	0
T29	186564	22622	0	0
T30	416328	60358	0	0
T59	361043	35437	0	0
T60	392020	38327	0	0
T94	454247	64105	0	0
T100	331952	73950	0	0
T116	179962	26284	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	295510316	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	295510316	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	295510316	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	840	840	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T94	1	1	0	0
T100	1	1	0	0
T116	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295593825	26689989	0	0
DepthKnown_A	295593825	295510316	0	0
RvalidKnown_A	295593825	295510316	0	0
WreadyKnown_A	295593825	295510316	0	0
gen_passthru_fifo.paramCheckPass	840	840	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	26689989	0	0
T1	138066	14685	0	0
T2	93452	8214	0	0
T3	227035	19506	0	0
T29	186564	17362	0	0
T30	416328	51282	0	0
T59	361043	31007	0	0
T60	392020	34754	0	0
T94	454247	60866	0	0
T100	331952	43919	0	0
T116	179962	22064	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	295510316	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	295510316	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	295510316	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	840	840	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T94	1	1	0	0
T100	1	1	0	0
T116	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295593825	20739926	0	0
DepthKnown_A	295593825	295510316	0	0
RvalidKnown_A	295593825	295510316	0	0
WreadyKnown_A	295593825	295510316	0	0
gen_passthru_fifo.paramCheckPass	840	840	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	20739926	0	0
T1	138066	4773	0	0
T2	93452	6388	0	0
T3	227035	24140	0	0
T29	186564	12368	0	0
T30	416328	43403	0	0
T59	361043	32540	0	0
T60	392020	32565	0	0
T94	454247	58135	0	0
T100	331952	53028	0	0
T116	179962	18548	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	295510316	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	295510316	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	295510316	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	840	840	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T94	1	1	0	0
T100	1	1	0	0
T116	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295593825	20250954	0	0
DepthKnown_A	295593825	295510316	0	0
RvalidKnown_A	295593825	295510316	0	0
WreadyKnown_A	295593825	295510316	0	0
gen_passthru_fifo.paramCheckPass	840	840	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	20250954	0	0
T1	138066	4597	0	0
T2	93452	6277	0	0
T3	227035	23938	0	0
T29	186564	12085	0	0
T30	416328	42995	0	0
T59	361043	32218	0	0
T60	392020	32414	0	0
T94	454247	57981	0	0
T100	331952	50196	0	0
T116	179962	18347	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	295510316	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	295510316	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	295510316	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	840	840	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T94	1	1	0	0
T100	1	1	0	0
T116	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	381392789	91992	0	0
DepthKnown_A	381392789	381297777	0	0
RvalidKnown_A	381392789	381297777	0	0
WreadyKnown_A	381392789	381297777	0	0
gen_passthru_fifo.paramCheckPass	2731	2731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	91992	0	0
T1	138066	48	0	0
T2	93452	13	0	0
T3	227035	53	0	0
T29	186564	32	0	0
T30	416328	48	0	0
T59	361043	23	0	0
T60	392020	33	0	0
T94	454247	13	0	0
T100	331952	21	0	0
T116	179962	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2731	2731	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T94	1	1	0	0
T100	1	1	0	0
T116	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	381392789	92397	0	0
DepthKnown_A	381392789	381297777	0	0
RvalidKnown_A	381392789	381297777	0	0
WreadyKnown_A	381392789	381297777	0	0
gen_passthru_fifo.paramCheckPass	2731	2731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	92397	0	0
T1	138066	48	0	0
T2	93452	13	0	0
T3	227035	53	0	0
T29	186564	32	0	0
T30	416328	48	0	0
T59	361043	23	0	0
T60	392020	33	0	0
T94	454247	13	0	0
T100	331952	21	0	0
T116	179962	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2731	2731	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T94	1	1	0	0
T100	1	1	0	0
T116	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	381392789	45906	0	0
DepthKnown_A	381392789	381297777	0	0
RvalidKnown_A	381392789	381297777	0	0
WreadyKnown_A	381392789	381297777	0	0
gen_passthru_fifo.paramCheckPass	2731	2731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	45906	0	0
T1	138066	47	0	0
T2	93452	12	0	0
T3	227035	52	0	0
T29	186564	30	0	0
T30	416328	41	0	0
T59	361043	20	0	0
T60	392020	32	0	0
T94	454247	12	0	0
T100	331952	12	0	0
T116	179962	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2731	2731	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T94	1	1	0	0
T100	1	1	0	0
T116	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	381392789	45906	0	0
DepthKnown_A	381392789	381297777	0	0
RvalidKnown_A	381392789	381297777	0	0
WreadyKnown_A	381392789	381297777	0	0
gen_passthru_fifo.paramCheckPass	2731	2731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	45906	0	0
T1	138066	47	0	0
T2	93452	12	0	0
T3	227035	52	0	0
T29	186564	30	0	0
T30	416328	41	0	0
T59	361043	20	0	0
T60	392020	32	0	0
T94	454247	12	0	0
T100	331952	12	0	0
T116	179962	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2731	2731	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T94	1	1	0	0
T100	1	1	0	0
T116	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	381392789	46086	0	0
DepthKnown_A	381392789	381297777	0	0
RvalidKnown_A	381392789	381297777	0	0
WreadyKnown_A	381392789	381297777	0	0
gen_passthru_fifo.paramCheckPass	2731	2731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	46086	0	0
T1	138066	1	0	0
T2	93452	1	0	0
T3	227035	1	0	0
T29	186564	2	0	0
T30	416328	7	0	0
T59	361043	3	0	0
T60	392020	1	0	0
T94	454247	1	0	0
T100	331952	9	0	0
T116	179962	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2731	2731	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T94	1	1	0	0
T100	1	1	0	0
T116	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	381392789	46491	0	0
DepthKnown_A	381392789	381297777	0	0
RvalidKnown_A	381392789	381297777	0	0
WreadyKnown_A	381392789	381297777	0	0
gen_passthru_fifo.paramCheckPass	2731	2731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	46491	0	0
T1	138066	1	0	0
T2	93452	1	0	0
T3	227035	1	0	0
T29	186564	2	0	0
T30	416328	7	0	0
T59	361043	3	0	0
T60	392020	1	0	0
T94	454247	1	0	0
T100	331952	9	0	0
T116	179962	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381392789	381297777	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2731	2731	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T94	1	1	0	0
T100	1	1	0	0
T116	1	1	0	0