Unified Coverage Report :: Module

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00


Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T215,T208,T44	Yes	T215,T208,T44	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T215,T208,T44	Yes	T215,T208,T44	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T63,T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T66,T67,*T68	Yes	T66,T67,T68	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	INPUT
tl_i.a_valid	Yes	Yes	T62,T215,T208	Yes	T62,T215,T208	INPUT
tl_o.a_ready	Yes	Yes	T62,T215,T208	Yes	T62,T215,T208	OUTPUT
tl_o.d_error	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T215,T208,T185	Yes	T215,T208,T185	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T215,T208,T185	Yes	T62,T215,T208	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T215,T208,T185	Yes	T62,T215,T208	OUTPUT
tl_o.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T63,T64,*T65	Yes	T63,T64,T65	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	T215,T208,*T185	Yes	T215,T208,T185	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T62,T215,T208	Yes	T62,T215,T208	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T693,T324	Yes	T62,T693,T324	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T693,T324	Yes	T62,T693,T324	OUTPUT
cio_rx_i	Yes	Yes	T29,T30,T31	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T215,T208,T185	Yes	T215,T208,T185	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T215,T208,T185	Yes	T215,T208,T185	OUTPUT
intr_rx_watermark_o	Yes	Yes	T215,T208,T185	Yes	T215,T208,T185	OUTPUT
intr_tx_empty_o	Yes	Yes	T215,T208,T185	Yes	T215,T208,T185	OUTPUT
intr_rx_overflow_o	Yes	Yes	T215,T208,T185	Yes	T215,T208,T185	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_break_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_timeout_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00


Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T215,T44,T216	Yes	T215,T44,T216	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T215,T44,T216	Yes	T215,T44,T216	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T63,T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T66,T67,*T68	Yes	T66,T67,T68	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	INPUT
tl_i.a_valid	Yes	Yes	T62,T215,T44	Yes	T62,T215,T44	INPUT
tl_o.a_ready	Yes	Yes	T62,T215,T216	Yes	T62,T215,T216	OUTPUT
tl_o.d_error	Yes	Yes	T64,T79,T113	Yes	T63,T64,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T215,T216,T164	Yes	T215,T216,T164	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T215,T216,T304	Yes	T62,T215,T216	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T215,T216,T304	Yes	T62,T215,T216	OUTPUT
tl_o.d_sink	Yes	Yes	T63,T64,T79	Yes	T63,T64,T70	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T64,T79,*T113	Yes	T63,T64,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T63,T64,T79	Yes	T63,T64,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	T215,T216,*T304	Yes	T215,T216,T304	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T62,T215,T216	Yes	T62,T215,T216	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T693,T83	Yes	T62,T693,T83	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T693,T83	Yes	T62,T693,T83	OUTPUT
cio_rx_i	Yes	Yes	T29,T30,T31	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T215,T216,T164	Yes	T215,T216,T164	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T215,T216,T164	Yes	T215,T216,T164	OUTPUT
intr_rx_watermark_o	Yes	Yes	T215,T216,T164	Yes	T215,T216,T164	OUTPUT
intr_tx_empty_o	Yes	Yes	T215,T216,T304	Yes	T215,T216,T304	OUTPUT
intr_rx_overflow_o	Yes	Yes	T215,T216,T304	Yes	T215,T216,T304	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_break_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_timeout_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00


Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T63,T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T66,T67,*T68	Yes	T66,T67,T68	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	INPUT
tl_i.a_valid	Yes	Yes	T62,T208,T209	Yes	T62,T208,T209	INPUT
tl_o.a_ready	Yes	Yes	T62,T208,T209	Yes	T62,T208,T209	OUTPUT
tl_o.d_error	Yes	Yes	T64,T79,T113	Yes	T64,T79,T113	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T208,T209,T143	Yes	T62,T208,T209	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T208,T209,T143	Yes	T62,T208,T209	OUTPUT
tl_o.d_sink	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T64,T79,*T113	Yes	T63,T64,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T64,T70,T113	Yes	T63,T64,T70	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	T208,T209,*T210	Yes	T208,T209,T210	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T62,T208,T209	Yes	T62,T208,T209	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T324,T321	Yes	T62,T324,T321	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T84,T85,T142	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T142	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T324,T321	Yes	T62,T324,T321	OUTPUT
cio_rx_i	Yes	Yes	T208,T209,T210	Yes	T208,T10,T209	INPUT
cio_tx_o	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	OUTPUT
intr_rx_watermark_o	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	OUTPUT
intr_tx_empty_o	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	OUTPUT
intr_rx_overflow_o	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_break_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_timeout_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00


Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T185,T186,T286	Yes	T185,T186,T286	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T185,T186,T286	Yes	T185,T186,T286	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T63,T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T66,T67,*T68	Yes	T66,T67,T68	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	INPUT
tl_i.a_valid	Yes	Yes	T62,T185,T143	Yes	T62,T185,T143	INPUT
tl_o.a_ready	Yes	Yes	T62,T185,T143	Yes	T62,T185,T143	OUTPUT
tl_o.d_error	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T185,T186,T286	Yes	T185,T186,T286	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T185,T143,T186	Yes	T62,T185,T143	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T185,T143,T186	Yes	T62,T185,T143	OUTPUT
tl_o.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T63,T64,*T70	Yes	T63,T64,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	T185,T186,*T286	Yes	T185,T186,T286	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T62,T185,T143	Yes	T62,T185,T143	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T83,T694	Yes	T62,T83,T694	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T83,T694	Yes	T62,T83,T694	OUTPUT
cio_rx_i	Yes	Yes	T185,T186,T301	Yes	T185,T186,T301	INPUT
cio_tx_o	Yes	Yes	T185,T186,T301	Yes	T185,T186,T301	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T185,T186,T286	Yes	T185,T186,T286	OUTPUT
intr_rx_watermark_o	Yes	Yes	T185,T186,T286	Yes	T185,T186,T286	OUTPUT
intr_tx_empty_o	Yes	Yes	T185,T186,T286	Yes	T185,T186,T286	OUTPUT
intr_rx_overflow_o	Yes	Yes	T185,T186,T286	Yes	T185,T186,T286	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_break_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_timeout_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00


Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T13,T123	Yes	T3,T13,T123	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T13,T123	Yes	T3,T13,T123	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T63,T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T66,T67,*T68	Yes	T66,T67,T68	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	INPUT
tl_i.a_valid	Yes	Yes	T3,T62,T143	Yes	T3,T62,T143	INPUT
tl_o.a_ready	Yes	Yes	T3,T62,T143	Yes	T3,T62,T143	OUTPUT
tl_o.d_error	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T13,T123	Yes	T3,T13,T123	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T143,T13	Yes	T3,T62,T143	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T143,T13	Yes	T3,T62,T143	OUTPUT
tl_o.d_sink	Yes	Yes	T64,T65,T70	Yes	T63,T64,T65	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T64,T65,*T79	Yes	T63,T64,T65	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T64,T65,T70	Yes	T64,T65,T70	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	T3,T13,*T123	Yes	T3,T13,T123	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T62,T143	Yes	T3,T62,T143	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T83,T281	Yes	T62,T83,T281	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T83,T281	Yes	T62,T83,T281	OUTPUT
cio_rx_i	Yes	Yes	T3,T13,T123	Yes	T3,T13,T123	INPUT
cio_tx_o	Yes	Yes	T3,T13,T123	Yes	T3,T13,T123	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T13,T123	Yes	T3,T13,T123	OUTPUT
intr_rx_watermark_o	Yes	Yes	T3,T13,T123	Yes	T3,T13,T123	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T13,T123	Yes	T3,T13,T123	OUTPUT
intr_rx_overflow_o	Yes	Yes	T3,T13,T123	Yes	T3,T13,T123	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_break_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_timeout_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T286,T287,T253	Yes	T286,T287,T253	OUTPUT

*Tests covering at least one bit in the range

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.61	90.68		93.15			100.00	top_earlgrey

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children