Unified Coverage Report :: Module :: prim_mubi4_dec

Module : prim_mubi4_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_padring.u_prim_mubi4_dec	0.00	0.00

---

Module Instance : tb.dut.u_padring.u_prim_mubi4_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.02			96.02				u_padring

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_mubi4_dec

	Line No.	Total	Covered	Percent
TOTAL		1	0	0.00
CONT_ASSIGN	25	0	0
CONT_ASSIGN	37	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_dec.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_dec.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25		unreachable
37	0	1

Line Coverage for Instance : tb.dut.u_padring.u_prim_mubi4_dec

	Line No.	Total	Covered	Percent
TOTAL		1	0	0.00
CONT_ASSIGN	25	0	0
CONT_ASSIGN	37	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_dec.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_dec.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25		unreachable
37	0	1