Module Definition
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Module : prim_mubi4_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_padring.u_prim_mubi4_dec 0.00 0.00



Module Instance : tb.dut.u_padring.u_prim_mubi4_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.02 96.02 u_padring


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_mubi4_dec
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN2500
CONT_ASSIGN37100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_dec.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 unreachable
37 0 1

Line Coverage for Instance : tb.dut.u_padring.u_prim_mubi4_dec
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN2500
CONT_ASSIGN37100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_dec.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 unreachable
37 0 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%