Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.61	90.68		93.15			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T63,T65,T70	Yes	T63,T64,T65	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T70,T79,T113	Yes	T70,T79,T113	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T31,T131,T135	Yes	T31,T131,T135	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T31,T89,T131	Yes	T31,T89,T131	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T66,T231,T195	Yes	T66,T231,T195	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T66,T231,T195	Yes	T66,T231,T195	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T31,T88,T193	Yes	T31,T88,T193	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T46,T43,T192	Yes	T46,T43,T192	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T46,T43,T192	Yes	T46,T43,T192	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T46,T43,T192	Yes	T46,T43,T192	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T46,T43,T192	Yes	T46,T43,T192	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T46,T43,T192	Yes	T46,T43,T192	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T46,T43,T192	Yes	T46,T43,T192	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T46,*T43,*T192	Yes	T46,T43,T192	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T46,T43,T192	Yes	T46,T43,T192	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T63,T65,T70	Yes	T63,T64,T65	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T63,T64,T65	Yes	T63,T64,T70	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T65	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T64,T70,T79	Yes	T63,T64,T65	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T65	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T65	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T64,T70,*T79	Yes	T63,T64,T70	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T63,T64,T70	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T63,*T64,*T70	Yes	T64,T70,T79	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T67,T80,T81	Yes	T67,T80,T81	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T67,T80,T81	Yes	T67,T80,T81	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T67,T80,T81	Yes	T67,T80,T81	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T67,T80,T81	Yes	T67,T80,T81	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T67,T80,T81	Yes	T67,T80,T81	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T67,*T80,*T81	Yes	T67,T80,T81	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T67,T80,T81	Yes	T67,T80,T81	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T29,T30,T34	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T67,T80,T81	Yes	T67,T80,T81	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T67,T80,T81	Yes	T67,T80,T81	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T29,T30,T34	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T67,*T80,*T81	Yes	T67,T80,T81	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T29,T30,T34	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T67,T80,T81	Yes	T67,T80,T81	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T62,T76,T104	Yes	T62,T76,T104	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T364,T365	Yes	T62,T364,T365	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T62,T364,T365	Yes	T62,T364,T365	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T62,T76,T104	Yes	T62,T76,T104	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T62,T364,T365	Yes	T62,T364,T365	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T63,*T64,*T70	Yes	T63,T64,T70	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T62,T364,T365	Yes	T62,T364,T365	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T62,T364,T365	Yes	T62,T364,T365	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T64,T79,T113	Yes	T64,T65,T70	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T78,T244,T366	Yes	T78,T244,T366	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T63,T64,T70	Yes	T62,T76,T104	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T78,T244,T366	Yes	T62,T78,T244	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T64,T70,T79	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T64,*T79,*T113	Yes	T63,T64,T65	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T364,*T365,*T78	Yes	T364,T365,T78	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T62,T364,T365	Yes	T62,T364,T365	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T193,T131,T323	Yes	T193,T131,T323	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T62,T10,T11	Yes	T62,T10,T11	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T62,T10,T11	Yes	T62,T10,T11	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T10,T11	Yes	T62,T10,T11	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T62,T10,T11	Yes	T62,T10,T11	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T62,T10,T11	Yes	T62,T10,T11	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T62,T10,T11	Yes	T62,T10,T11	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T63,*T64,*T70	Yes	T63,T64,T70	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T12,T203,T204	Yes	T12,T203,T204	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T62,T10,T11	Yes	T62,T10,T11	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T62,T10,T11	Yes	T62,T10,T11	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T64,T79,T113	Yes	T64,T79,T113	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T11,T202	Yes	T10,T11,T202	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T11,T143	Yes	T62,T10,T11	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T11,T202	Yes	T10,T11,T202	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T63,T64,T79	Yes	T63,T64,T70	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T64,*T79,*T113	Yes	T63,T64,T70	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T11,*T202	Yes	T10,T11,T202	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T62,T10,T11	Yes	T62,T10,T11	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T62,T202,T344	Yes	T62,T202,T344	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T62,T202,T344	Yes	T62,T202,T344	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T202,T344	Yes	T62,T202,T344	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T62,T202,T344	Yes	T62,T202,T344	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T62,T202,T344	Yes	T62,T202,T344	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T62,T202,T344	Yes	T62,T202,T344	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T62,T202,T344	Yes	T62,T202,T344	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T62,T202,T344	Yes	T62,T202,T344	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T202,T344,T32	Yes	T202,T344,T32	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T202,T344,T32	Yes	T62,T202,T344	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T202,T344,T32	Yes	T202,T344,T32	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T202,*T344,*T32	Yes	T202,T344,T32	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T62,T202,T344	Yes	T62,T202,T344	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T62,T15,T16	Yes	T62,T15,T16	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T62,T15,T16	Yes	T62,T15,T16	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T15,T16	Yes	T62,T15,T16	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T62,T15,T16	Yes	T62,T15,T16	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T62,T15,T16	Yes	T62,T15,T16	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T62,T15,T16	Yes	T62,T15,T16	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T63,*T64,*T70	Yes	T63,T64,T70	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T63,T64,T79	Yes	T63,T64,T79	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T64,T79,T113	Yes	T64,T79,T113	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T62,T15,T16	Yes	T62,T15,T16	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T62,T15,T16	Yes	T62,T15,T16	INPUT
tl_usbdev_i.d_error	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T17,T202,T344	Yes	T17,T202,T344	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T202,T344	Yes	T17,T202,T344	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T62,T15,T16	Yes	T15,T16,T17	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T63,T64,T79	Yes	T63,T64,T70	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T64,*T70,*T79	Yes	T64,T70,T79	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T63,T64,T79	Yes	T63,T64,T79	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T62,*T15,*T16	Yes	T15,T16,T17	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T62,T15,T16	Yes	T62,T15,T16	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T195,*T196,*T63	Yes	T195,T196,T63	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T29,T30,T34	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T29,T30,T100	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T64,T70,T79	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T195,*T196,*T64	Yes	T195,T196,T63	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T195,T196,T63	Yes	T195,T196,T63	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T195,T196,T63	Yes	T195,T196,T63	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T195,T196,T63	Yes	T195,T196,T63	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T195,T196,T63	Yes	T195,T196,T63	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T195,T196,T63	Yes	T195,T196,T63	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T195,*T196,T63	Yes	T195,T196,T63	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T195,T196,T63	Yes	T195,T196,T63	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T195,T196,T63	Yes	T195,T196,T63	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T195,T196,T63	Yes	T195,T196,T63	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T195,T196,T63	Yes	T195,T196,T63	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T195,T196,T63	Yes	T195,T196,T64	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T195,*T196,T64	Yes	T195,T196,T63	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T65	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T195,*T196,*T63	Yes	T195,T196,T63	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T195,T196,T63	Yes	T195,T196,T63	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T3,T59	Yes	T1,T3,T59	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T29,T30,T34	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T62,T339,T317	Yes	T62,T339,T317	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T339,T317	Yes	T62,T339,T317	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T62,T339,T317	Yes	T62,T339,T317	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T62,T339,T317	Yes	T62,T339,T317	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T62,T339,T317	Yes	T62,T339,T317	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T195,*T196,*T63	Yes	T195,T196,T63	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T339,T317,T318	Yes	T339,T317,T318	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T62,T339,T317	Yes	T62,T339,T317	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T62,T339,T317	Yes	T62,T339,T317	INPUT
tl_hmac_i.d_error	Yes	Yes	T64,T70,T79	Yes	T63,T64,T70	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T339,T317,T318	Yes	T339,T317,T318	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T339,T317,T318	Yes	T339,T317,T318	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T62,T339,T317	Yes	T339,T317,T318	INPUT
tl_hmac_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T195,*T196,*T64	Yes	T195,T196,T63	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T63,T64,T70	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T62,*T339,*T317	Yes	T339,T317,T318	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T62,T339,T317	Yes	T62,T339,T317	INPUT
tl_kmac_o.d_ready	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T62,T98,T162	Yes	T62,T98,T162	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T30,T61,T62	Yes	T30,T61,T62	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T30,T61,T62	Yes	T30,T61,T62	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T62,T162,T77	Yes	T62,T162,T77	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T30,T61,T62	Yes	T30,T61,T62	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T195,*T196,*T63	Yes	T195,T196,T63	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T162,T197,T198	Yes	T162,T197,T198	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T30,T61,T62	Yes	T30,T61,T62	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T30,T61,T62	Yes	T30,T61,T62	INPUT
tl_kmac_i.d_error	Yes	Yes	T63,T70,T79	Yes	T63,T70,T79	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T30,T61,T98	Yes	T30,T61,T98	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T61,T98	Yes	T30,T61,T98	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T30,T61,T62	Yes	T162,T77,T5	INPUT
tl_kmac_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T195,*T196,*T64	Yes	T195,T196,T63	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T63,T64,T70	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T30,*T61,*T62	Yes	T162,T5,T197	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T30,T61,T62	Yes	T30,T61,T62	INPUT
tl_aes_o.d_ready	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T30,T62,T129	Yes	T30,T62,T129	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T30,T62,T129	Yes	T30,T62,T129	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T30,T62,T129	Yes	T30,T62,T129	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T30,T62,T129	Yes	T30,T62,T129	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T30,T62,T129	Yes	T30,T62,T129	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T66,*T196,*T63	Yes	T66,T196,T63	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T63,T64,T79	Yes	T63,T64,T79	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T63,T64,T113	Yes	T63,T64,T113	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T30,T62,T129	Yes	T30,T62,T129	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T30,T62,T129	Yes	T30,T62,T129	INPUT
tl_aes_i.d_error	Yes	Yes	T63,T64,T70	Yes	T63,T64,T65	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T30,T129,T133	Yes	T30,T129,T133	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T129,T133	Yes	T30,T62,T129	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T129,T133,T323	Yes	T30,T62,T129	INPUT
tl_aes_i.d_sink	Yes	Yes	T63,T64,T79	Yes	T63,T64,T65	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T66,*T196,*T63	Yes	T66,T196,T63	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T63,T64,T79	Yes	T63,T64,T65	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T30,*T129,*T133	Yes	T30,T129,T133	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T30,T62,T129	Yes	T30,T62,T129	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T195,*T196,*T63	Yes	T195,T196,T63	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T94,T30	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T64,T70,T79	Yes	T63,T64,T70	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T195,*T196,*T64	Yes	T195,T196,T63	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T64,T70,T79	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T94,*T30,*T60	Yes	T94,T30,T60	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T29,T94,T30	Yes	T29,T94,T30	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T66,*T195,*T196	Yes	T66,T195,T196	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T64,T65,T70	Yes	T64,T65,T70	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T29,T94,T30	Yes	T29,T94,T30	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T94,T30	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T66,*T195,*T196	Yes	T66,T195,T196	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T29,*T94,*T30	Yes	T29,T94,T30	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T195,*T196,*T63	Yes	T195,T196,T63	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T94,T30	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T29,T94,T30	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T64,T70,T79	Yes	T63,T64,T70	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T195,*T196,*T64	Yes	T195,T196,T64	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T94,*T30,*T60	Yes	T94,T30,T60	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T29,T94,T30	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T195,*T196,*T63	Yes	T195,T196,T63	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	INPUT
tl_edn1_i.d_error	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	INPUT
tl_edn1_i.d_sink	Yes	Yes	T64,T65,T70	Yes	T63,T64,T70	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T195,*T196,*T64	Yes	T195,T196,T63	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T64,T70,T79	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T94,*T30,*T60	Yes	T94,T30,T60	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T3,T59,T29	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T3,T59,T60	Yes	T3,T59,T60	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T59,T60	Yes	T3,T59,T60	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T3,T59,T60	Yes	T3,T59,T60	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T3,T59,T60	Yes	T3,T59,T60	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T3,T59,T60	Yes	T3,T59,T60	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T63,*T64,*T70	Yes	T63,T64,T70	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T63,T64,T79	Yes	T63,T64,T79	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T3,T59,T60	Yes	T3,T59,T60	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T3,T59,T60	Yes	T3,T59,T60	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T63,T64,T79	Yes	T63,T64,T79	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T3,T59,T60	Yes	T3,T59,T60	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T59,T60	Yes	T3,T59,T60	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T3,T59,T60	Yes	T3,T59,T60	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T63,T64,T79	Yes	T63,T64,T79	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T63,*T64,*T79	Yes	T63,T64,T70	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T63,T64,T79	Yes	T63,T64,T79	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T3,*T59,*T60	Yes	T3,T59,T60	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T3,T59,T60	Yes	T3,T59,T60	INPUT
tl_otbn_o.d_ready	Yes	Yes	T29,T94,T30	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T68,*T69,*T231	Yes	T68,T69,T231	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	INPUT
tl_otbn_i.d_error	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	INPUT
tl_otbn_i.d_sink	Yes	Yes	T64,T65,T79	Yes	T63,T64,T70	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T68,*T69,*T231	Yes	T68,T69,T231	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T64,T79,T113	Yes	T64,T70,T79	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T94,*T30,*T60	Yes	T94,T30,T60	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T94,T30,T60	Yes	T94,T30,T60	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T30,T62,T98	Yes	T30,T62,T98	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T30,T61,T62	Yes	T30,T61,T62	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T30,T61,T62	Yes	T30,T61,T62	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T30,T62,T98	Yes	T30,T62,T98	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T30,T61,T62	Yes	T30,T61,T62	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T195,*T196,*T63	Yes	T195,T196,T63	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T30,T61,T62	Yes	T30,T61,T62	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T30,T61,T62	Yes	T30,T61,T62	INPUT
tl_keymgr_i.d_error	Yes	Yes	T64,T79,T113	Yes	T64,T79,T113	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T30,T98,T77	Yes	T30,T98,T77	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T98,T47	Yes	T30,T62,T98	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T30,T98,T47	Yes	T30,T62,T98	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T64,T70,T79	Yes	T64,T65,T70	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T195,*T196,*T64	Yes	T195,T196,T63	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T64,T79,T113	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T30,*T98,*T77	Yes	T30,T61,T98	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T30,T61,T62	Yes	T30,T61,T62	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T63,*T64,*T70	Yes	T63,T64,T70	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T63,T64,T79	Yes	T63,T64,T79	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T59,T30,T100	Yes	T59,T30,T100	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T59,T100,T116	Yes	T59,T100,T116	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T63,*T64,*T79	Yes	T63,T64,T79	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T62,T76,T125	Yes	T62,T76,T125	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T76,T125	Yes	T62,T76,T125	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T62,T76,T125	Yes	T62,T76,T125	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T62,T76,T125	Yes	T62,T76,T125	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T62,T76,T125	Yes	T62,T76,T125	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T64,T65,T70	Yes	T64,T65,T70	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T62,T76,T125	Yes	T62,T76,T125	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T62,T76,T125	Yes	T62,T76,T125	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T152,T155,T156	Yes	T152,T155,T156	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T125,T146,T147	Yes	T62,T76,T125	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T125,T146,T147	Yes	T62,T76,T125	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T79	Yes	T63,T64,T65	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T125,*T146,*T147	Yes	T125,T146,T147	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T62,T76,T125	Yes	T62,T76,T125	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T29,T30,T34	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range