Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.61	90.68		93.15			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T193,T131,T323	Yes	T193,T131,T323	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T215,T44,T216	Yes	T215,T44,T216	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T215,T44,T216	Yes	T215,T44,T216	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T62,T215,T44	Yes	T62,T215,T44	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T62,T215,T216	Yes	T62,T215,T216	INPUT
tl_uart0_i.d_error	Yes	Yes	T64,T79,T113	Yes	T63,T64,T79	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T215,T216,T164	Yes	T215,T216,T164	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T215,T216,T304	Yes	T62,T215,T216	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T215,T216,T304	Yes	T62,T215,T216	INPUT
tl_uart0_i.d_sink	Yes	Yes	T63,T64,T79	Yes	T63,T64,T70	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T64,*T79,*T113	Yes	T63,T64,T79	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T63,T64,T79	Yes	T63,T64,T79	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T215,*T216,*T304	Yes	T215,T216,T304	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T62,T215,T216	Yes	T62,T215,T216	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T62,T208,T209	Yes	T62,T208,T209	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T62,T208,T209	Yes	T62,T208,T209	INPUT
tl_uart1_i.d_error	Yes	Yes	T64,T79,T113	Yes	T64,T79,T113	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T208,T209,T143	Yes	T62,T208,T209	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T208,T209,T143	Yes	T62,T208,T209	INPUT
tl_uart1_i.d_sink	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T64,*T79,*T113	Yes	T63,T64,T70	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T64,T70,T113	Yes	T63,T64,T70	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T208,*T209,*T210	Yes	T208,T209,T210	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T62,T208,T209	Yes	T62,T208,T209	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T185,T186,T286	Yes	T185,T186,T286	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T185,T186,T286	Yes	T185,T186,T286	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T62,T185,T143	Yes	T62,T185,T143	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T62,T185,T143	Yes	T62,T185,T143	INPUT
tl_uart2_i.d_error	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T185,T186,T286	Yes	T185,T186,T286	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T185,T143,T186	Yes	T62,T185,T143	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T185,T143,T186	Yes	T62,T185,T143	INPUT
tl_uart2_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T63,*T64,*T70	Yes	T63,T64,T70	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T185,*T186,*T286	Yes	T185,T186,T286	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T62,T185,T143	Yes	T62,T185,T143	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T3,T13,T123	Yes	T3,T13,T123	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T3,T13,T123	Yes	T3,T13,T123	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T3,T62,T143	Yes	T3,T62,T143	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T3,T62,T143	Yes	T3,T62,T143	INPUT
tl_uart3_i.d_error	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T3,T13,T123	Yes	T3,T13,T123	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T143,T13	Yes	T3,T62,T143	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T3,T143,T13	Yes	T3,T62,T143	INPUT
tl_uart3_i.d_sink	Yes	Yes	T64,T65,T70	Yes	T63,T64,T65	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T79	Yes	T63,T64,T65	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T64,T65,T70	Yes	T64,T65,T70	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T3,*T13,*T123	Yes	T3,T13,T123	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T3,T62,T143	Yes	T3,T62,T143	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T194,T132,T202	Yes	T194,T132,T202	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T194,T132,T202	Yes	T194,T132,T202	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T194,T62,T132	Yes	T194,T62,T132	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T194,T62,T132	Yes	T194,T62,T132	INPUT
tl_i2c0_i.d_error	Yes	Yes	T64,T65,T70	Yes	T64,T65,T70	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T194,T132,T288	Yes	T194,T132,T288	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T194,T132,T143	Yes	T194,T62,T132	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T194,T132,T143	Yes	T194,T62,T132	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T195,*T196,*T64	Yes	T195,T196,T63	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T64,T65,T70	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T194,*T132,*T202	Yes	T194,T132,T202	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T194,T62,T132	Yes	T194,T62,T132	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T214,T202,T297	Yes	T214,T202,T297	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T214,T202,T297	Yes	T214,T202,T297	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T62,T214,T143	Yes	T62,T214,T143	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T62,T214,T143	Yes	T62,T214,T143	INPUT
tl_i2c1_i.d_error	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T214,T297,T288	Yes	T214,T297,T288	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T214,T143,T202	Yes	T62,T214,T143	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T214,T143,T202	Yes	T62,T214,T143	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T64,T70,T79	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T195,*T196,*T64	Yes	T195,T196,T63	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T64,T70,T79	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T214,*T202,*T297	Yes	T214,T202,T297	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T62,T214,T143	Yes	T62,T214,T143	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T59,T202,T344	Yes	T59,T202,T344	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T59,T202,T344	Yes	T59,T202,T344	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T59,T62,T143	Yes	T59,T62,T143	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T59,T62,T143	Yes	T59,T62,T143	INPUT
tl_i2c2_i.d_error	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T59,T303,T288	Yes	T59,T303,T288	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T143,T202	Yes	T59,T62,T143	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T59,T143,T202	Yes	T59,T62,T143	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T65	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T195,*T196,*T64	Yes	T195,T196,T63	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T63,T64,T79	Yes	T63,T64,T65	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T59,*T202,*T344	Yes	T59,T202,T344	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T59,T62,T143	Yes	T59,T62,T143	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T213,T139,T140	Yes	T213,T139,T140	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T213,T139,T140	Yes	T213,T139,T140	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T62,T213,T76	Yes	T62,T213,T76	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T62,T213,T76	Yes	T62,T213,T76	INPUT
tl_pattgen_i.d_error	Yes	Yes	T63,T64,T70	Yes	T64,T70,T79	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T213,T139,T140	Yes	T213,T139,T140	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T213,T139,T140	Yes	T62,T213,T76	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T213,T139,T140	Yes	T62,T213,T76	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T64,T79,*T113	Yes	T63,T64,T70	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T213,*T139,*T140	Yes	T213,T139,T140	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T62,T213,T76	Yes	T62,T213,T76	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T106,T704,T720	Yes	T106,T704,T720	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T106,T704,T720	Yes	T106,T704,T720	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T106,T62,T76	Yes	T106,T62,T76	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T106,T62,T76	Yes	T106,T62,T76	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T64,T65,T79	Yes	T64,T70,T79	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T106,T704,T720	Yes	T106,T704,T720	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T106,T704,T720	Yes	T106,T62,T76	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T106,T704,T720	Yes	T106,T62,T76	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	T64,*T65,*T79	Yes	T64,T70,T79	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T64,T70,T113	Yes	T64,T70,T113	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T106,*T704,*T720	Yes	T106,T704,T720	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T106,T62,T76	Yes	T106,T62,T76	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	Yes	Yes	T64,T65,T79	Yes	T64,T65,T79	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T14,T23,T24	Yes	T14,T23,T24	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T106,T14,T23	Yes	T106,T62,T14	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T106,T14,T23	Yes	T106,T62,T14	INPUT
tl_gpio_i.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T195,*T196,*T64	Yes	T195,T196,T64	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T64,T65,T79	Yes	T64,T65,T70	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T29,*T30,*T34	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T11,T37,T202	Yes	T11,T37,T202	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T11,T37,T202	Yes	T11,T37,T202	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T62,T11,T37	Yes	T62,T11,T37	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T62,T11,T37	Yes	T62,T11,T37	INPUT
tl_spi_device_i.d_error	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T11,T37,T202	Yes	T11,T37,T202	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T11,T37,T202	Yes	T11,T37,T202	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T62,T11,T37	Yes	T11,T37,T202	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T63,*T64,*T79	Yes	T63,T64,T70	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T62,*T11,*T37	Yes	T11,T37,T202	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T62,T11,T37	Yes	T62,T11,T37	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T106,T237,T235	Yes	T106,T237,T235	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T106,T237,T235	Yes	T106,T237,T235	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T106,T237,T62	Yes	T106,T237,T62	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T106,T237,T62	Yes	T106,T237,T62	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T237,T235,T236	Yes	T237,T235,T236	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T106,T237,T235	Yes	T106,T237,T62	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T106,T237,T235	Yes	T106,T237,T62	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T64,*T79,*T113	Yes	T63,T64,T70	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T106,*T237,*T235	Yes	T106,T237,T235	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T106,T237,T62	Yes	T106,T237,T62	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T34,T106	Yes	T1,T34,T106	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T34,T106	Yes	T1,T34,T106	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T1,T30,T34	Yes	T1,T30,T34	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T1,T30,T34	Yes	T1,T30,T34	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T63,T64,T70	Yes	T64,T70,T79	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T34,T106,T4	Yes	T34,T106,T4	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T106,T4	Yes	T30,T34,T106	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T34,T106,T4	Yes	T30,T34,T106	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T64,*T79,*T113	Yes	T63,T64,T70	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T34,*T106,*T4	Yes	T1,T34,T106	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T1,T30,T34	Yes	T1,T30,T34	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T63,*T64,*T79	Yes	T63,T64,T70	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T60	Yes	T1,T3,T60	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T3,T30	Yes	T1,T3,T30	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T63,T64,T70	Yes	T63,T64,T79	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T215	Yes	T1,T3,T215	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T29	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T3,T29	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T66,*T196,*T63	Yes	T66,T196,T63	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T60	Yes	T1,T3,T60	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T63,T64,T65	Yes	T63,T64,T70	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T70	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T64,*T70,*T113	Yes	T63,T64,T65	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T65	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T64,T65,T70	Yes	T63,T64,T65	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T63,T64,T65	Yes	T64,T65,T70	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T79	Yes	T64,T65,T70	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T64,T65,T70	Yes	T64,T65,T70	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T29,*T30,*T61	Yes	T29,T30,T61	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T29,T30,T34	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T65	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T29,T30,T34	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T64,*T65,T79	Yes	T63,T64,T70	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T70	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T29,T30,T34	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T31,T61,T62	Yes	T31,T61,T62	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T31,T61,T62	Yes	T31,T61,T62	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T31,T61,T62	Yes	T31,T61,T62	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T31,T61,T62	Yes	T31,T61,T62	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T5,T71,T72	Yes	T31,T61,T73	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T74,T75	Yes	T62,T5,T76	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T77,T5,T78	Yes	T31,T61,T62	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T67,*T80,*T81	Yes	T67,T80,T81	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T64,T65,T70	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T77,*T5,*T78	Yes	T31,T61,T73	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T31,T61,T62	Yes	T31,T61,T62	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T63,T64,T79	Yes	T63,T64,T79	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T174,T16,T175	Yes	T174,T16,T175	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T174,T16,T175	Yes	T62,T174,T16	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T63,T64,T79	Yes	T64,T65,T79	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T63,*T64,*T79	Yes	T63,T64,T70	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T64,T79,T113	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T29,*T30,*T31	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T30,T31,T106	Yes	T30,T31,T106	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T30,T31,T106	Yes	T30,T31,T106	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T30,T31,T106	Yes	T30,T31,T106	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T30,T31,T106	Yes	T30,T31,T106	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T63,T64,T65	Yes	T64,T65,T70	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T30,T31,T106	Yes	T30,T31,T106	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T31,T106	Yes	T30,T31,T106	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T31,T106,T88	Yes	T30,T31,T106	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T64,T65,T70	Yes	T63,T64,T65	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T66,*T196,*T64	Yes	T66,T196,T64	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T64,T65,T70	Yes	T64,T65,T70	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T30,*T31,*T106	Yes	T30,T31,T106	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T30,T31,T106	Yes	T30,T31,T106	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T148,T149,T125	Yes	T148,T149,T125	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T148,T149,T125	Yes	T148,T149,T125	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T62,T148,T149	Yes	T62,T148,T149	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T62,T148,T149	Yes	T62,T148,T149	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T63,T64,T79	Yes	T63,T64,T70	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T148,T149,T125	Yes	T148,T149,T125	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T148,T149,T125	Yes	T62,T148,T149	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T148,T149,T125	Yes	T62,T148,T149	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T79	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T64,*T79,*T113	Yes	T63,T64,T70	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T64,T79,T113	Yes	T64,T79,T113	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T148,*T149,*T125	Yes	T148,T149,T125	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T62,T148,T149	Yes	T62,T148,T149	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T29,T30,T34	Yes	T29,T30,T34	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T29,T30,T31	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T29,T30,T34	Yes	T29,T30,T34	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T29,T30,T34	Yes	T29,T30,T34	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T64,T70,T79	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T68,*T69,*T231	Yes	T68,T69,T231	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T31,T106,T237	Yes	T31,T106,T237	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T31,T106,T237	Yes	T31,T106,T237	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T31,T106,T237	Yes	T31,T106,T237	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T31,T106,T237	Yes	T31,T106,T237	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T63,T64,T65	Yes	T63,T64,T70	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T31,T106,T237	Yes	T31,T106,T237	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T106,T237	Yes	T31,T106,T237	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T31,T106,T237	Yes	T31,T106,T237	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T63,T64,T65	Yes	T63,T64,T113	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T66,*T196,*T64	Yes	T66,T196,T63	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T31,*T106,*T237	Yes	T31,T106,T237	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T31,T106,T237	Yes	T31,T106,T237	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T34,T35,T99	Yes	T34,T35,T99	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T34,T35,T99	Yes	T34,T35,T99	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T34,T62,T35	Yes	T34,T62,T35	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T34,T62,T35	Yes	T34,T62,T35	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T64,T70,T79	Yes	T64,T70,T113	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T34,T35,T99	Yes	T34,T35,T99	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T35,T99	Yes	T34,T62,T35	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T34,T35,T99	Yes	T34,T62,T35	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T64,*T79,*T113	Yes	T63,T64,T70	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T63,T64,T70	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T34,*T35,*T99	Yes	T34,T35,T99	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T34,T62,T35	Yes	T34,T62,T35	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T106,T47,T15	Yes	T106,T47,T15	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T106,T47,T15	Yes	T106,T47,T15	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T106,T62,T47	Yes	T106,T62,T47	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T106,T62,T47	Yes	T106,T62,T47	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T63,T64,T79	Yes	T64,T79,T113	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T15,T16,T167	Yes	T47,T15,T16	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T106,T47,T15	Yes	T106,T62,T47	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T106,T47,T15	Yes	T106,T62,T47	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T63,T64,T79	Yes	T63,T64,T70	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T66,*T196,*T64	Yes	T66,T196,T63	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T64,T70,T79	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T106,*T15,*T16	Yes	T106,T47,T15	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T106,T62,T47	Yes	T106,T62,T47	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T63,T64,T79	Yes	T64,T79,T113	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	T64,*T79,T113	Yes	T63,T64,T70	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T64,T70,T79	Yes	T64,T70,T79	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T64,*T70,*T79	Yes	T63,T64,T70	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range