Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.32 94.12 89.29 100.00 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 84.62 100.00 100.00 u_edn_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00

Line Coverage for Module : prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Module : prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 591187650 2955 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 591187650 2955 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 591187650 2955 0 0
T1 138066 1 0 0
T2 93452 1 0 0
T3 227035 1 0 0
T7 88926 0 0 0
T29 186564 2 0 0
T30 416328 3 0 0
T59 361043 2 0 0
T60 392020 1 0 0
T94 454247 1 0 0
T100 331952 5 0 0
T105 173846 0 0 0
T116 179962 7 0 0
T150 101974 4 0 0
T151 0 4 0 0
T153 0 4 0 0
T185 111743 0 0 0
T212 104868 0 0 0
T216 110021 0 0 0
T268 0 4 0 0
T269 0 8 0 0
T270 0 3 0 0
T271 240826 0 0 0
T272 505637 0 0 0
T273 646978 0 0 0
T274 86574 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 591187650 2955 0 0
T1 138066 1 0 0
T2 93452 1 0 0
T3 227035 1 0 0
T7 88926 0 0 0
T29 186564 2 0 0
T30 416328 3 0 0
T59 361043 2 0 0
T60 392020 1 0 0
T94 454247 1 0 0
T100 331952 5 0 0
T105 173846 0 0 0
T116 179962 7 0 0
T150 101974 4 0 0
T151 0 4 0 0
T153 0 4 0 0
T185 111743 0 0 0
T212 104868 0 0 0
T216 110021 0 0 0
T268 0 4 0 0
T269 0 8 0 0
T270 0 3 0 0
T271 240826 0 0 0
T272 505637 0 0 0
T273 646978 0 0 0
T274 86574 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 295593825 27 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 295593825 27 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 295593825 27 0 0
T7 88926 0 0 0
T105 173846 0 0 0
T150 101974 4 0 0
T151 0 4 0 0
T153 0 4 0 0
T185 111743 0 0 0
T212 104868 0 0 0
T216 110021 0 0 0
T268 0 4 0 0
T269 0 8 0 0
T270 0 3 0 0
T271 240826 0 0 0
T272 505637 0 0 0
T273 646978 0 0 0
T274 86574 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 295593825 27 0 0
T7 88926 0 0 0
T105 173846 0 0 0
T150 101974 4 0 0
T151 0 4 0 0
T153 0 4 0 0
T185 111743 0 0 0
T212 104868 0 0 0
T216 110021 0 0 0
T268 0 4 0 0
T269 0 8 0 0
T270 0 3 0 0
T271 240826 0 0 0
T272 505637 0 0 0
T273 646978 0 0 0
T274 86574 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 295593825 2928 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 295593825 2928 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 295593825 2928 0 0
T1 138066 1 0 0
T2 93452 1 0 0
T3 227035 1 0 0
T29 186564 2 0 0
T30 416328 3 0 0
T59 361043 2 0 0
T60 392020 1 0 0
T94 454247 1 0 0
T100 331952 5 0 0
T116 179962 7 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 295593825 2928 0 0
T1 138066 1 0 0
T2 93452 1 0 0
T3 227035 1 0 0
T29 186564 2 0 0
T30 416328 3 0 0
T59 361043 2 0 0
T60 392020 1 0 0
T94 454247 1 0 0
T100 331952 5 0 0
T116 179962 7 0 0

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