Unified Coverage Report :: Module :: rv_timer

Module : rv_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_timer	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.61	90.68		93.15			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : rv_timer

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	292	292	100.00
Total Bits 0->1	146	146	100.00
Total Bits 1->0	146	146	100.00

Ports	30	30	100.00
Port Bits	292	292	100.00
Port Bits 0->1	146	146	100.00
Port Bits 1->0	146	146	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T29,T30,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T106,T237,T235	Yes	T106,T237,T235	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T106,T237,T235	Yes	T106,T237,T235	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[8:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_address[19:9]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T66,*T67,*T68	Yes	T66,T67,T68	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T65	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T66,T68,T69	Yes	T66,T68,T69	INPUT
tl_i.a_valid	Yes	Yes	T106,T237,T62	Yes	T106,T237,T62	INPUT
tl_o.a_ready	Yes	Yes	T106,T237,T62	Yes	T106,T237,T62	OUTPUT
tl_o.d_error	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T237,T235,T236	Yes	T237,T235,T236	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T106,T237,T235	Yes	T106,T237,T62	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T106,T237,T235	Yes	T106,T237,T62	OUTPUT
tl_o.d_sink	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T64,*T79,*T113	Yes	T63,T64,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T63,T64,T70	Yes	T63,T64,T70	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T106,*T237,*T235	Yes	T106,T237,T235	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T106,T237,T62	Yes	T106,T237,T62	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T83,T695	Yes	T62,T83,T695	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T85,T115	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T85,T115	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T83,T695	Yes	T62,T83,T695	OUTPUT
intr_timer_expired_hart0_timer0_o	Yes	Yes	T235,T236,T139	Yes	T235,T236,T139	OUTPUT

*Tests covering at least one bit in the range