Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T150,T151,T268
0	1	Covered	T150,T151,T268
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T150,T151,T268
1	Covered	T150,T151,T268

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T150,T151,T268
1	Covered	T150,T151,T268

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T150,T151,T268
1	1	Covered	T150,T151,T268

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T150,T151,T268
1	0	Covered	T150,T151,T268
1	1	Covered	T150,T151,T268

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T150,T151,T268

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T150,T151,T268
0	Covered	T150,T151,T268

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T150,T151,T268
0	Covered	T150,T151,T268

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	591187650	574400494	0	0
CheckNGreaterZero_A	1680	1680	0	0
GntImpliesReady_A	591187650	5430	0	0
GntImpliesValid_A	591187650	5430	0	0
GrantKnown_A	591187650	574400494	0	0
IdxKnown_A	591187650	574400494	0	0
IndexIsCorrect_A	591187650	5430	0	0
NoReadyValidNoGrant_A	591187650	0	0	0
Priority_A	591187650	5430	0	0
ReadyAndValidImplyGrant_A	591187650	5430	0	0
ReqAndReadyImplyGrant_A	591187650	5430	0	0
ReqImpliesValid_A	591187650	5430	0	0
ValidKnown_A	591187650	574400494	0	0
gen_data_port_assertion.DataFlow_A	591187650	5430	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591187650	574400494	0	0
T1	276132	276022	0	0
T2	186904	186802	0	0
T3	454070	453954	0	0
T29	373128	372916	0	0
T30	832656	832430	0	0
T59	722086	721970	0	0
T60	784040	783916	0	0
T94	908494	908378	0	0
T100	663904	663802	0	0
T116	359924	359800	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680	1680	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T29	2	2	0	0
T30	2	2	0	0
T59	2	2	0	0
T60	2	2	0	0
T94	2	2	0	0
T100	2	2	0	0
T116	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591187650	5430	0	0
T7	177852	0	0	0
T105	347692	0	0	0
T150	203948	1804	0	0
T151	0	1810	0	0
T185	223486	0	0	0
T212	209736	0	0	0
T216	220042	0	0	0
T268	0	1816	0	0
T271	481652	0	0	0
T272	1011274	0	0	0
T273	1293956	0	0	0
T274	173148	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591187650	5430	0	0
T7	177852	0	0	0
T105	347692	0	0	0
T150	203948	1804	0	0
T151	0	1810	0	0
T185	223486	0	0	0
T212	209736	0	0	0
T216	220042	0	0	0
T268	0	1816	0	0
T271	481652	0	0	0
T272	1011274	0	0	0
T273	1293956	0	0	0
T274	173148	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591187650	574400494	0	0
T1	276132	276022	0	0
T2	186904	186802	0	0
T3	454070	453954	0	0
T29	373128	372916	0	0
T30	832656	832430	0	0
T59	722086	721970	0	0
T60	784040	783916	0	0
T94	908494	908378	0	0
T100	663904	663802	0	0
T116	359924	359800	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591187650	574400494	0	0
T1	276132	276022	0	0
T2	186904	186802	0	0
T3	454070	453954	0	0
T29	373128	372916	0	0
T30	832656	832430	0	0
T59	722086	721970	0	0
T60	784040	783916	0	0
T94	908494	908378	0	0
T100	663904	663802	0	0
T116	359924	359800	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591187650	5430	0	0
T7	177852	0	0	0
T105	347692	0	0	0
T150	203948	1804	0	0
T151	0	1810	0	0
T185	223486	0	0	0
T212	209736	0	0	0
T216	220042	0	0	0
T268	0	1816	0	0
T271	481652	0	0	0
T272	1011274	0	0	0
T273	1293956	0	0	0
T274	173148	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591187650	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591187650	5430	0	0
T7	177852	0	0	0
T105	347692	0	0	0
T150	203948	1804	0	0
T151	0	1810	0	0
T185	223486	0	0	0
T212	209736	0	0	0
T216	220042	0	0	0
T268	0	1816	0	0
T271	481652	0	0	0
T272	1011274	0	0	0
T273	1293956	0	0	0
T274	173148	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591187650	5430	0	0
T7	177852	0	0	0
T105	347692	0	0	0
T150	203948	1804	0	0
T151	0	1810	0	0
T185	223486	0	0	0
T212	209736	0	0	0
T216	220042	0	0	0
T268	0	1816	0	0
T271	481652	0	0	0
T272	1011274	0	0	0
T273	1293956	0	0	0
T274	173148	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591187650	5430	0	0
T7	177852	0	0	0
T105	347692	0	0	0
T150	203948	1804	0	0
T151	0	1810	0	0
T185	223486	0	0	0
T212	209736	0	0	0
T216	220042	0	0	0
T268	0	1816	0	0
T271	481652	0	0	0
T272	1011274	0	0	0
T273	1293956	0	0	0
T274	173148	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591187650	5430	0	0
T7	177852	0	0	0
T105	347692	0	0	0
T150	203948	1804	0	0
T151	0	1810	0	0
T185	223486	0	0	0
T212	209736	0	0	0
T216	220042	0	0	0
T268	0	1816	0	0
T271	481652	0	0	0
T272	1011274	0	0	0
T273	1293956	0	0	0
T274	173148	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591187650	574400494	0	0
T1	276132	276022	0	0
T2	186904	186802	0	0
T3	454070	453954	0	0
T29	373128	372916	0	0
T30	832656	832430	0	0
T59	722086	721970	0	0
T60	784040	783916	0	0
T94	908494	908378	0	0
T100	663904	663802	0	0
T116	359924	359800	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591187650	5430	0	0
T7	177852	0	0	0
T105	347692	0	0	0
T150	203948	1804	0	0
T151	0	1810	0	0
T185	223486	0	0	0
T212	209736	0	0	0
T216	220042	0	0	0
T268	0	1816	0	0
T271	481652	0	0	0
T272	1011274	0	0	0
T273	1293956	0	0	0
T274	173148	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T150,T151,T268
0	1	Covered	T150,T151,T268
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T150,T151,T268
1	Covered	T150,T151,T268

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T150,T151,T268
1	Covered	T150,T151,T268

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T150,T151,T268
1	1	Covered	T150,T151,T268

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T150,T151,T268
1	0	Covered	T150,T151,T268
1	1	Covered	T150,T151,T268

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T150,T151,T268

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T150,T151,T268
0	Covered	T150,T151,T268

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T150,T151,T268
0	Covered	T150,T151,T268

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	295593825	287200247	0	0
CheckNGreaterZero_A	840	840	0	0
GntImpliesReady_A	295593825	4392	0	0
GntImpliesValid_A	295593825	4392	0	0
GrantKnown_A	295593825	287200247	0	0
IdxKnown_A	295593825	287200247	0	0
IndexIsCorrect_A	295593825	4392	0	0
NoReadyValidNoGrant_A	295593825	0	0	0
Priority_A	295593825	4392	0	0
ReadyAndValidImplyGrant_A	295593825	4392	0	0
ReqAndReadyImplyGrant_A	295593825	4392	0	0
ReqImpliesValid_A	295593825	4392	0	0
ValidKnown_A	295593825	287200247	0	0
gen_data_port_assertion.DataFlow_A	295593825	4392	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	287200247	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840	840	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T94	1	1	0	0
T100	1	1	0	0
T116	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	4392	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	1458	0	0
T151	0	1464	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	1470	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	4392	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	1458	0	0
T151	0	1464	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	1470	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	287200247	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	287200247	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	4392	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	1458	0	0
T151	0	1464	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	1470	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	4392	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	1458	0	0
T151	0	1464	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	1470	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	4392	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	1458	0	0
T151	0	1464	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	1470	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	4392	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	1458	0	0
T151	0	1464	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	1470	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	4392	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	1458	0	0
T151	0	1464	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	1470	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	287200247	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	4392	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	1458	0	0
T151	0	1464	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	1470	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T150,T151,T268
0	1	Covered	T150,T151,T268
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T150,T151,T268
1	Covered	T150,T151,T268

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T150,T151,T268
1	Covered	T150,T151,T268

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T150,T151,T268
1	1	Covered	T150,T151,T268

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T150,T151,T268
1	0	Covered	T150,T151,T268
1	1	Covered	T150,T151,T268

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T150,T151,T268

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T150,T151,T268
0	Covered	T150,T151,T268

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T150,T151,T268
0	Covered	T150,T151,T268

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	295593825	287200247	0	0
CheckNGreaterZero_A	840	840	0	0
GntImpliesReady_A	295593825	1038	0	0
GntImpliesValid_A	295593825	1038	0	0
GrantKnown_A	295593825	287200247	0	0
IdxKnown_A	295593825	287200247	0	0
IndexIsCorrect_A	295593825	1038	0	0
NoReadyValidNoGrant_A	295593825	0	0	0
Priority_A	295593825	1038	0	0
ReadyAndValidImplyGrant_A	295593825	1038	0	0
ReqAndReadyImplyGrant_A	295593825	1038	0	0
ReqImpliesValid_A	295593825	1038	0	0
ValidKnown_A	295593825	287200247	0	0
gen_data_port_assertion.DataFlow_A	295593825	1038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	287200247	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	840	840	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T94	1	1	0	0
T100	1	1	0	0
T116	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	1038	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	346	0	0
T151	0	346	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	346	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	1038	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	346	0	0
T151	0	346	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	346	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	287200247	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	287200247	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	1038	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	346	0	0
T151	0	346	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	346	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	1038	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	346	0	0
T151	0	346	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	346	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	1038	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	346	0	0
T151	0	346	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	346	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	1038	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	346	0	0
T151	0	346	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	346	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	1038	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	346	0	0
T151	0	346	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	346	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	287200247	0	0
T1	138066	138011	0	0
T2	93452	93401	0	0
T3	227035	226977	0	0
T29	186564	186458	0	0
T30	416328	416215	0	0
T59	361043	360985	0	0
T60	392020	391958	0	0
T94	454247	454189	0	0
T100	331952	331901	0	0
T116	179962	179900	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295593825	1038	0	0
T7	88926	0	0	0
T105	173846	0	0	0
T150	101974	346	0	0
T151	0	346	0	0
T185	111743	0	0	0
T212	104868	0	0	0
T216	110021	0	0	0
T268	0	346	0	0
T271	240826	0	0	0
T272	505637	0	0	0
T273	646978	0	0	0
T274	86574	0	0	0