Unified Coverage Report :: Module :: chip_earlgrey_asic

Module : chip_earlgrey_asic

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.63	76.19	100.00	95.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	91.56	76.19	100.00	98.48

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	76.19	100.00	98.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.58	95.32	93.80	91.97		94.43	97.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
top_earlgrey	94.34	95.26	93.33	91.88		94.21	97.02
u_ast	92.94			92.94
u_padring	98.97	99.40	99.80	96.02		99.60	100.00
u_prim_usb_diff_rx	96.30	100.00	88.89			100.00

Line Coverage for Module : chip_earlgrey_asic

	Line No.	Total	Covered	Percent
TOTAL		21	16	76.19
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	786	1	0	0.00
CONT_ASSIGN	797	1	0	0.00
CONT_ASSIGN	822	1	0	0.00
CONT_ASSIGN	829	1	0	0.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	847	1	1	100.00
CONT_ASSIGN	851	1	0	0.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	1023	1	1	100.00
CONT_ASSIGN	1040	1	1	100.00
CONT_ASSIGN	1041	1	1	100.00
CONT_ASSIGN	1042	1	1	100.00
CONT_ASSIGN	1043	1	1	100.00
CONT_ASSIGN	1047	1	1	100.00
CONT_ASSIGN	1048	1	1	100.00
CONT_ASSIGN	1049	1	1	100.00
CONT_ASSIGN	1050	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
212	1	1
213	1	1
786	0	1
797	0	1
822	0	1
829	0	1
836	1	1
839	1	1
845	1	1
847	1	1
851	0	1
854	1	1
1023	1	1
1040	1	1
1041	1	1
1042	1	1
1043	1	1
1047	1	1
1048	1	1
1049	1	1
1050	1	1

---

Cond Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T106,T4

---

Toggle Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Totals	70	64	91.43
Total Bits	140	134	95.71
Total Bits 0->1	70	70	100.00
Total Bits 1->0	70	64	91.43

Ports	70	64	91.43
Port Bits	140	134	95.71
Port Bits 0->1	70	70	100.00
Port Bits 1->0	70	64	91.43

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
POR_N	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INOUT
USB_P	Yes	Yes	T17,T21,T22	Yes	T17,T21,T22	INOUT
USB_N	Yes	Yes	T17,T21,T22	Yes	T17,T7,T8	INOUT
CC1	No	No		Yes	T7,T8,T9	INOUT
CC2	No	No		Yes	T7,T8,T9	INOUT
FLASH_TEST_VOLT	No	No		Yes	T7,T8,T9	INOUT
FLASH_TEST_MODE0	No	No		Yes	T7,T8,T9	INOUT
FLASH_TEST_MODE1	No	No		Yes	T7,T8,T9	INOUT
OTP_EXT_VOLT	No	No		Yes	T7,T8,T9	INOUT
SPI_HOST_D0	Yes	Yes	T10,T11,T12	Yes	T10,T7,T11	INOUT
SPI_HOST_D1	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INOUT
SPI_HOST_D2	Yes	Yes	T11,T12,T203	Yes	T11,T12,T203	INOUT
SPI_HOST_D3	Yes	Yes	T11,T12,T203	Yes	T11,T12,T203	INOUT
SPI_HOST_CLK	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INOUT
SPI_HOST_CS_L	Yes	Yes	T10,T11,T12	Yes	T10,T7,T11	INOUT
SPI_DEV_D0	Yes	Yes	T11,T37,T12	Yes	T11,T37,T12	INOUT
SPI_DEV_D1	Yes	Yes	T11,T37,T12	Yes	T7,T11,T37	INOUT
SPI_DEV_D2	Yes	Yes	T11,T12,T203	Yes	T11,T12,T203	INOUT
SPI_DEV_D3	Yes	Yes	T11,T12,T203	Yes	T7,T11,T12	INOUT
SPI_DEV_CLK	Yes	Yes	T11,T37,T12	Yes	T7,T11,T37	INOUT
SPI_DEV_CS_L	Yes	Yes	T7,T11,T49	Yes	T7,T11,T8	INOUT
IOR8	Yes	Yes	T18,T206,T207	Yes	T18,T206,T207	INOUT
IOR9	Yes	Yes	T18,T206,T19	Yes	T34,T35,T18	INOUT
IOA0	Yes	Yes	T3,T13,T14	Yes	T3,T8,T13	INOUT
IOA1	Yes	Yes	T3,T13,T14	Yes	T3,T13,T14	INOUT
IOA2	Yes	Yes	T106,T14,T23	Yes	T106,T14,T23	INOUT
IOA3	Yes	Yes	T14,T23,T24	Yes	T8,T14,T23	INOUT
IOA4	Yes	Yes	T185,T14,T186	Yes	T185,T14,T186	INOUT
IOA5	Yes	Yes	T185,T14,T186	Yes	T185,T14,T186	INOUT
IOA6	Yes	Yes	T14,T23,T24	Yes	T7,T8,T14	INOUT
IOA7	Yes	Yes	T194,T132,T37	Yes	T194,T132,T37	INOUT
IOA8	Yes	Yes	T194,T132,T14	Yes	T194,T132,T14	INOUT
IOB0	Yes	Yes	T32,T26,T27	Yes	T8,T32,T26	INOUT
IOB1	Yes	Yes	T32,T26,T27	Yes	T32,T26,T27	INOUT
IOB2	Yes	Yes	T26,T27,T28	Yes	T8,T26,T27	INOUT
IOB3	Yes	Yes	T18,T206,T207	Yes	T206,T207,T212	INOUT
IOB4	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	INOUT
IOB5	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	INOUT
IOB6	Yes	Yes	T18,T206,T207	Yes	T206,T207,T7	INOUT
IOB7	Yes	Yes	T15,T16,T50	Yes	T34,T35,T18	INOUT
IOB8	Yes	Yes	T206,T207,T212	Yes	T206,T207,T212	INOUT
IOB9	Yes	Yes	T18,T213,T214	Yes	T18,T213,T214	INOUT
IOB10	Yes	Yes	T106,T213,T214	Yes	T106,T213,T214	INOUT
IOB11	Yes	Yes	T59,T106,T14	Yes	T59,T106,T14	INOUT
IOB12	Yes	Yes	T59,T106,T14	Yes	T59,T106,T14	INOUT
IOC0	Yes	Yes	T72,T40,T275	Yes	T7,T8,T276	INOUT
IOC1	Yes	Yes	T72,T275,T276	Yes	T7,T9,T276	INOUT
IOC2	Yes	Yes	T72,T275,T276	Yes	T7,T8,T9	INOUT
IOC3	Yes	Yes	T215,T7,T216	Yes	T215,T7,T216	INOUT
IOC4	Yes	Yes	T215,T216,T164	Yes	T215,T216,T164	INOUT
IOC5	Yes	Yes	T46,T48,T43	Yes	T48,T43,T192	INOUT
IOC6	Yes	Yes	T82,T157,T158	Yes	T82,T157,T7	INOUT
IOC7	Yes	Yes	T206,T207,T212	Yes	T18,T206,T207	INOUT
IOC8	Yes	Yes	T46,T48,T43	Yes	T46,T48,T43	INOUT
IOC9	Yes	Yes	T34,T35,T207	Yes	T34,T35,T18	INOUT
IOC10	Yes	Yes	T106,T14,T23	Yes	T106,T14,T23	INOUT
IOC11	Yes	Yes	T106,T14,T23	Yes	T106,T7,T14	INOUT
IOC12	Yes	Yes	T106,T14,T23	Yes	T106,T14,T23	INOUT
IOR0	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	INOUT
IOR1	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	INOUT
IOR2	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	INOUT
IOR3	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	INOUT
IOR4	Yes	Yes	T46,T43,T14	Yes	T46,T47,T48	INOUT
IOR5	Yes	Yes	T18,T14,T23	Yes	T18,T14,T23	INOUT
IOR6	Yes	Yes	T14,T23,T24	Yes	T18,T8,T14	INOUT
IOR7	Yes	Yes	T14,T23,T24	Yes	T14,T23,T24	INOUT
IOR10	Yes	Yes	T14,T23,T24	Yes	T7,T8,T14	INOUT
IOR11	Yes	Yes	T14,T23,T24	Yes	T8,T14,T23	INOUT
IOR12	Yes	Yes	T14,T23,T24	Yes	T7,T14,T23	INOUT
IOR13	Yes	Yes	T15,T206,T16	Yes	T15,T206,T16	INOUT

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		21	16	76.19
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	786	1	0	0.00
CONT_ASSIGN	797	1	0	0.00
CONT_ASSIGN	822	1	0	0.00
CONT_ASSIGN	829	1	0	0.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	847	1	1	100.00
CONT_ASSIGN	851	1	0	0.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	1023	1	1	100.00
CONT_ASSIGN	1040	1	1	100.00
CONT_ASSIGN	1041	1	1	100.00
CONT_ASSIGN	1042	1	1	100.00
CONT_ASSIGN	1043	1	1	100.00
CONT_ASSIGN	1047	1	1	100.00
CONT_ASSIGN	1048	1	1	100.00
CONT_ASSIGN	1049	1	1	100.00
CONT_ASSIGN	1050	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
212	1	1
213	1	1
786	0	1
797	0	1
822	0	1
829	0	1
836	1	1
839	1	1
845	1	1
847	1	1
851	0	1
854	1	1
1023	1	1
1040	1	1
1041	1	1
1042	1	1
1043	1	1
1047	1	1
1048	1	1
1049	1	1
1050	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T106,T4

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	66	64	96.97
Total Bits	132	130	98.48
Total Bits 0->1	66	66	100.00
Total Bits 1->0	66	64	96.97

Ports	66	64	96.97
Port Bits	132	130	98.48
Port Bits 0->1	66	66	100.00
Port Bits 1->0	66	64	96.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
POR_N	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INOUT
USB_P	Yes	Yes	T17,T21,T22	Yes	T17,T21,T22	INOUT
USB_N	Yes	Yes	T17,T21,T22	Yes	T17,T7,T8	INOUT
CC1	No	No		Yes	T7,T8,T9	INOUT
CC2	No	No		Yes	T7,T8,T9	INOUT
FLASH_TEST_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0	Yes	Yes	T10,T11,T12	Yes	T10,T7,T11	INOUT
SPI_HOST_D1	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INOUT
SPI_HOST_D2	Yes	Yes	T11,T12,T203	Yes	T11,T12,T203	INOUT
SPI_HOST_D3	Yes	Yes	T11,T12,T203	Yes	T11,T12,T203	INOUT
SPI_HOST_CLK	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INOUT
SPI_HOST_CS_L	Yes	Yes	T10,T11,T12	Yes	T10,T7,T11	INOUT
SPI_DEV_D0	Yes	Yes	T11,T37,T12	Yes	T11,T37,T12	INOUT
SPI_DEV_D1	Yes	Yes	T11,T37,T12	Yes	T7,T11,T37	INOUT
SPI_DEV_D2	Yes	Yes	T11,T12,T203	Yes	T11,T12,T203	INOUT
SPI_DEV_D3	Yes	Yes	T11,T12,T203	Yes	T7,T11,T12	INOUT
SPI_DEV_CLK	Yes	Yes	T11,T37,T12	Yes	T7,T11,T37	INOUT
SPI_DEV_CS_L	Yes	Yes	T7,T11,T49	Yes	T7,T11,T8	INOUT
IOR8	Yes	Yes	T18,T206,T207	Yes	T18,T206,T207	INOUT
IOR9	Yes	Yes	T18,T206,T19	Yes	T34,T35,T18	INOUT
IOA0	Yes	Yes	T3,T13,T14	Yes	T3,T8,T13	INOUT
IOA1	Yes	Yes	T3,T13,T14	Yes	T3,T13,T14	INOUT
IOA2	Yes	Yes	T106,T14,T23	Yes	T106,T14,T23	INOUT
IOA3	Yes	Yes	T14,T23,T24	Yes	T8,T14,T23	INOUT
IOA4	Yes	Yes	T185,T14,T186	Yes	T185,T14,T186	INOUT
IOA5	Yes	Yes	T185,T14,T186	Yes	T185,T14,T186	INOUT
IOA6	Yes	Yes	T14,T23,T24	Yes	T7,T8,T14	INOUT
IOA7	Yes	Yes	T194,T132,T37	Yes	T194,T132,T37	INOUT
IOA8	Yes	Yes	T194,T132,T14	Yes	T194,T132,T14	INOUT
IOB0	Yes	Yes	T32,T26,T27	Yes	T8,T32,T26	INOUT
IOB1	Yes	Yes	T32,T26,T27	Yes	T32,T26,T27	INOUT
IOB2	Yes	Yes	T26,T27,T28	Yes	T8,T26,T27	INOUT
IOB3	Yes	Yes	T18,T206,T207	Yes	T206,T207,T212	INOUT
IOB4	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	INOUT
IOB5	Yes	Yes	T208,T209,T210	Yes	T208,T209,T210	INOUT
IOB6	Yes	Yes	T18,T206,T207	Yes	T206,T207,T7	INOUT
IOB7	Yes	Yes	T15,T16,T50	Yes	T34,T35,T18	INOUT
IOB8	Yes	Yes	T206,T207,T212	Yes	T206,T207,T212	INOUT
IOB9	Yes	Yes	T18,T213,T214	Yes	T18,T213,T214	INOUT
IOB10	Yes	Yes	T106,T213,T214	Yes	T106,T213,T214	INOUT
IOB11	Yes	Yes	T59,T106,T14	Yes	T59,T106,T14	INOUT
IOB12	Yes	Yes	T59,T106,T14	Yes	T59,T106,T14	INOUT
IOC0	Yes	Yes	T72,T40,T275	Yes	T7,T8,T276	INOUT
IOC1	Yes	Yes	T72,T275,T276	Yes	T7,T9,T276	INOUT
IOC2	Yes	Yes	T72,T275,T276	Yes	T7,T8,T9	INOUT
IOC3	Yes	Yes	T215,T7,T216	Yes	T215,T7,T216	INOUT
IOC4	Yes	Yes	T215,T216,T164	Yes	T215,T216,T164	INOUT
IOC5	Yes	Yes	T46,T48,T43	Yes	T48,T43,T192	INOUT
IOC6	Yes	Yes	T82,T157,T158	Yes	T82,T157,T7	INOUT
IOC7	Yes	Yes	T206,T207,T212	Yes	T18,T206,T207	INOUT
IOC8	Yes	Yes	T46,T48,T43	Yes	T46,T48,T43	INOUT
IOC9	Yes	Yes	T34,T35,T207	Yes	T34,T35,T18	INOUT
IOC10	Yes	Yes	T106,T14,T23	Yes	T106,T14,T23	INOUT
IOC11	Yes	Yes	T106,T14,T23	Yes	T106,T7,T14	INOUT
IOC12	Yes	Yes	T106,T14,T23	Yes	T106,T14,T23	INOUT
IOR0	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	INOUT
IOR1	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	INOUT
IOR2	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	INOUT
IOR3	Yes	Yes	T46,T47,T48	Yes	T46,T47,T48	INOUT
IOR4	Yes	Yes	T46,T43,T14	Yes	T46,T47,T48	INOUT
IOR5	Yes	Yes	T18,T14,T23	Yes	T18,T14,T23	INOUT
IOR6	Yes	Yes	T14,T23,T24	Yes	T18,T8,T14	INOUT
IOR7	Yes	Yes	T14,T23,T24	Yes	T14,T23,T24	INOUT
IOR10	Yes	Yes	T14,T23,T24	Yes	T7,T8,T14	INOUT
IOR11	Yes	Yes	T14,T23,T24	Yes	T8,T14,T23	INOUT
IOR12	Yes	Yes	T14,T23,T24	Yes	T7,T14,T23	INOUT
IOR13	Yes	Yes	T15,T206,T16	Yes	T15,T206,T16	INOUT