Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3701500	1			T62	1490		T63	304		T64	707
values[2]	747052	1			T62	423		T63	129		T64	72
values[3]	103470	1			T63	63		T64	1		T242	1
values[4]	53223	1			T63	5		T240	295		T479	167
values[5]	35371	1			T63	1		T240	176		T479	84
values[6]	26408	1			T240	133		T479	51		T497	7
values[7]	21388	1			T240	98		T479	47		T497	7
values[8]	18620	1			T240	90		T479	36		T497	7
values[9]	16763	1			T240	52		T479	28		T497	7
values[10]	15787	1			T240	51		T479	27		T497	7
values[11]	14628	1			T240	37		T479	34		T497	7
values[12]	13660	1			T240	38		T479	43		T497	7
values[13]	13169	1			T240	44		T479	26		T497	7
values[14]	12685	1			T240	23		T479	27		T497	7
values[15]	12355	1			T240	31		T479	17		T497	7
values[16]	11835	1			T240	29		T479	26		T497	8
values[17]	11299	1			T240	44		T479	22		T497	7
values[18]	10690	1			T240	31		T479	18		T497	7
values[19]	10601	1			T240	28		T479	14		T497	7
values[20]	10145	1			T240	25		T479	19		T497	7
values[21]	9980	1			T240	10		T479	22		T497	7
values[22]	9901	1			T240	10		T479	16		T497	7
values[23]	9422	1			T240	8		T479	15		T497	7
values[24]	9352	1			T240	5		T479	18		T497	7
values[25]	9116	1			T240	4		T479	14		T497	7
values[26]	8371	1			T240	14		T479	21		T497	7
values[27]	7972	1			T240	7		T479	30		T497	7
values[28]	7472	1			T240	9		T479	30		T497	8
values[29]	7086	1			T240	8		T479	34		T497	7
values[30]	6411	1			T240	6		T479	16		T497	7
values[31]	5987	1			T240	9		T479	8		T497	7
values[32]	5466	1			T240	9		T479	13		T497	7
values[33]	5110	1			T240	11		T479	12		T497	7
values[34]	4784	1			T240	4		T479	11		T497	7
values[35]	4500	1			T240	9		T479	9		T497	7
values[36]	4355	1			T240	7		T479	13		T497	7
values[37]	4056	1			T240	3		T479	9		T497	7
values[38]	3804	1			T240	3		T479	15		T497	7
values[39]	3690	1			T240	8		T479	7		T497	8
values[40]	3403	1			T240	9		T479	11		T497	8
values[41]	3285	1			T240	9		T479	9		T497	7
values[42]	3365	1			T240	13		T479	9		T497	7
values[43]	3174	1			T240	4		T479	10		T497	7
values[44]	3121	1			T240	4		T479	9		T497	7
values[45]	3091	1			T240	6		T479	7		T497	7
values[46]	3109	1			T240	6		T479	6		T497	7
values[47]	2988	1			T240	9		T479	11		T497	7
values[48]	2945	1			T240	9		T479	4		T497	7
values[49]	2850	1			T240	15		T479	7		T497	7
values[50]	2823	1			T240	12		T479	13		T497	7
values[51]	2777	1			T240	8		T479	6		T497	7
values[52]	2753	1			T240	21		T479	6		T497	7
values[53]	2663	1			T240	13		T479	13		T497	7
values[54]	2619	1			T240	15		T479	13		T497	7
values[55]	2554	1			T240	10		T479	6		T497	7
values[56]	2501	1			T240	7		T479	5		T497	7
values[57]	2449	1			T240	9		T479	9		T497	7
values[58]	2409	1			T240	4		T479	7		T497	7
values[59]	2537	1			T240	4		T479	10		T497	7
values[60]	2416	1			T240	3		T479	8		T497	7
values[61]	2797	1			T240	3		T479	9		T497	7
values[62]	4298	1			T240	6		T479	15		T497	7
values[63]	16518	1			T240	32		T479	74		T497	49
values[64]	218948	1			T240	113		T479	270		T497	1299

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4760977	1			T62	1562		T63	270		T64	657
values[2]	795404	1			T62	414		T63	67		T64	57
values[3]	75652	1			T62	15		T63	22		T64	1
values[4]	13453	1			T62	4		T63	7		T240	2
values[5]	5019	1			T63	2		T240	2		T479	2
values[6]	3043	1			T63	1		T240	2		T479	3
values[7]	2173	1			T240	2		T479	2		T497	1
values[8]	1786	1			T240	2		T479	6		T497	1
values[9]	1556	1			T240	1		T479	5		T497	1
values[10]	1411	1			T240	6		T479	3		T396	20
values[11]	1340	1			T240	1		T479	6		T396	30
values[12]	1219	1			T240	2		T479	6		T396	36
values[13]	1139	1			T240	1		T479	12		T396	19
values[14]	1033	1			T240	1		T479	2		T396	22
values[15]	974	1			T240	1		T479	2		T396	10
values[16]	990	1			T240	1		T479	3		T396	1
values[17]	927	1			T240	6		T479	2		T480	2
values[18]	901	1			T240	3		T479	3		T480	2
values[19]	844	1			T240	1		T479	5		T480	2
values[20]	829	1			T240	1		T479	6		T480	2
values[21]	788	1			T240	1		T479	4		T480	2
values[22]	718	1			T240	2		T479	5		T480	2
values[23]	741	1			T240	2		T479	5		T480	2
values[24]	673	1			T240	2		T479	3		T480	2
values[25]	687	1			T240	2		T479	2		T480	2
values[26]	676	1			T240	1		T479	2		T480	2
values[27]	701	1			T240	1		T479	3		T480	2
values[28]	692	1			T240	2		T479	2		T480	2
values[29]	619	1			T240	4		T479	5		T480	2
values[30]	619	1			T240	2		T479	6		T480	2
values[31]	575	1			T240	1		T479	2		T480	2
values[32]	626	1			T240	2		T479	2		T480	2
values[33]	536	1			T240	2		T479	3		T480	2
values[34]	525	1			T240	3		T479	3		T480	2
values[35]	504	1			T240	1		T479	5		T480	2
values[36]	508	1			T240	1		T479	2		T480	2
values[37]	555	1			T240	1		T479	3		T480	2
values[38]	518	1			T240	1		T479	2		T480	2
values[39]	489	1			T240	1		T479	2		T480	2
values[40]	478	1			T240	1		T479	2		T480	2
values[41]	427	1			T240	3		T479	2		T480	2
values[42]	418	1			T240	1		T479	3		T480	2
values[43]	413	1			T240	1		T479	3		T480	2
values[44]	388	1			T240	1		T479	4		T480	2
values[45]	431	1			T240	1		T479	4		T480	3
values[46]	414	1			T240	1		T479	3		T480	2
values[47]	382	1			T240	1		T479	7		T480	2
values[48]	377	1			T240	2		T479	5		T480	2
values[49]	389	1			T240	2		T479	3		T480	2
values[50]	377	1			T240	1		T479	6		T480	2
values[51]	385	1			T240	1		T479	3		T480	2
values[52]	381	1			T240	3		T479	5		T480	2
values[53]	377	1			T240	7		T479	7		T480	2
values[54]	384	1			T240	4		T479	10		T480	3
values[55]	340	1			T240	4		T479	4		T480	2
values[56]	352	1			T240	3		T479	5		T480	2
values[57]	331	1			T240	1		T479	2		T480	2
values[58]	336	1			T240	1		T479	4		T480	2
values[59]	357	1			T240	1		T479	7		T480	2
values[60]	359	1			T240	1		T479	4		T480	2
values[61]	397	1			T240	1		T479	4		T480	2
values[62]	569	1			T240	7		T479	7		T480	2
values[63]	3086	1			T240	68		T479	73		T480	3
values[64]	27465	1			T240	95		T479	165		T480	87

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	596950	1			T62	14		T63	3		T64	5
values[2]	2627647	1			T62	1338		T63	39		T64	699
values[3]	1155166	1			T62	297		T63	304		T64	78
values[4]	143965	1			T62	1		T63	58		T240	669
values[5]	72939	1			T63	3		T240	390		T479	221
values[6]	47578	1			T240	282		T479	128		T497	7
values[7]	35004	1			T240	176		T479	71		T497	7
values[8]	27676	1			T240	154		T479	27		T497	7
values[9]	22976	1			T240	123		T479	30		T497	7
values[10]	20144	1			T240	92		T479	23		T497	7
values[11]	18258	1			T240	81		T479	36		T497	7
values[12]	16984	1			T240	61		T479	22		T497	8
values[13]	15721	1			T240	54		T479	30		T497	7
values[14]	15238	1			T240	47		T479	30		T497	7
values[15]	14408	1			T240	39		T479	28		T497	7
values[16]	13725	1			T240	32		T479	30		T497	7
values[17]	12970	1			T240	28		T479	30		T497	7
values[18]	12820	1			T240	23		T479	45		T497	7
values[19]	12261	1			T240	17		T479	35		T497	7
values[20]	11780	1			T240	10		T479	27		T497	7
values[21]	11737	1			T240	28		T479	36		T497	7
values[22]	11705	1			T240	26		T479	41		T497	7
values[23]	11134	1			T240	33		T479	25		T497	7
values[24]	10622	1			T240	22		T479	13		T497	7
values[25]	10181	1			T240	7		T479	22		T497	7
values[26]	9628	1			T240	13		T479	17		T497	7
values[27]	9082	1			T240	9		T479	17		T497	7
values[28]	8749	1			T240	11		T479	16		T497	7
values[29]	8393	1			T240	8		T479	12		T497	7
values[30]	7510	1			T240	7		T479	14		T497	7
values[31]	6994	1			T240	7		T479	6		T497	7
values[32]	6255	1			T240	7		T479	8		T497	7
values[33]	5911	1			T240	6		T479	11		T497	7
values[34]	5574	1			T240	4		T479	9		T497	7
values[35]	5019	1			T240	9		T479	11		T497	7
values[36]	4734	1			T240	15		T479	5		T497	8
values[37]	4394	1			T240	6		T479	5		T497	7
values[38]	4167	1			T240	4		T479	5		T497	7
values[39]	3945	1			T240	7		T479	5		T497	7
values[40]	3935	1			T240	10		T479	15		T497	7
values[41]	3755	1			T240	11		T479	16		T497	7
values[42]	3752	1			T240	4		T479	14		T497	7
values[43]	3664	1			T240	10		T479	11		T497	7
values[44]	3630	1			T240	13		T479	16		T497	7
values[45]	3509	1			T240	8		T479	8		T497	7
values[46]	3496	1			T240	10		T479	13		T497	8
values[47]	3241	1			T240	14		T479	17		T497	7
values[48]	3218	1			T240	7		T479	7		T497	7
values[49]	3232	1			T240	4		T479	10		T497	7
values[50]	3138	1			T240	10		T479	8		T497	7
values[51]	3028	1			T240	8		T479	16		T497	7
values[52]	3065	1			T240	3		T479	13		T497	7
values[53]	2942	1			T240	5		T479	6		T497	7
values[54]	2955	1			T240	5		T479	4		T497	7
values[55]	2937	1			T240	5		T479	9		T497	7
values[56]	2853	1			T240	4		T479	5		T497	7
values[57]	2768	1			T240	6		T479	14		T497	7
values[58]	2793	1			T240	10		T479	5		T497	7
values[59]	2789	1			T240	6		T479	8		T497	8
values[60]	2690	1			T240	5		T479	5		T497	7
values[61]	2813	1			T240	6		T479	13		T497	7
values[62]	3977	1			T240	13		T479	11		T497	9
values[63]	17741	1			T240	31		T479	64		T497	14
values[64]	209358	1			T240	152		T479	217		T497	1172