Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2040780	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

21718489

1

T1

43584

T2

68791

T3

140627

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15372418	1			T1	33768		T2	62040		T3	76072
values[0x0]	6928123	1			T1	9816		T2	6751		T3	64555
values[0x1]	1458728	1			T1	79		T2	427		T3	3432

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	673077	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

23086192

1

T1

43663

T2

69218

T3

144059

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10635569	1			T1	21832		T2	34609		T3	72030
valid_sources[0x01]	10634805	1			T1	21831		T2	34609		T3	72029
valid_sources[0x02]	39322	1			T5	1		T807	4		T499	22
valid_sources[0x03]	40036	1			T807	6		T499	16		T364	520
valid_sources[0x04]	39642	1			T5	2		T807	15		T499	19
valid_sources[0x05]	40810	1			T5	1		T67	1		T51	1
valid_sources[0x06]	39390	1			T5	1		T51	1		T807	5
valid_sources[0x07]	39736	1			T5	1		T807	2		T499	22
valid_sources[0x08]	40699	1			T67	1		T807	4		T499	29
valid_sources[0x09]	40040	1			T67	1		T51	2		T807	8
valid_sources[0x0a]	39845	1			T5	2		T807	2		T499	23
valid_sources[0x0b]	39831	1			T5	1		T67	1		T807	8
valid_sources[0x0c]	41067	1			T67	1		T51	1		T807	14
valid_sources[0x0d]	39188	1			T5	1		T67	1		T807	7
valid_sources[0x0e]	41452	1			T807	5		T499	27		T364	346
valid_sources[0x0f]	43114	1			T67	2		T807	8		T499	25
valid_sources[0x10]	39838	1			T67	1		T807	7		T499	22
valid_sources[0x11]	40325	1			T5	3		T67	1		T807	1
valid_sources[0x12]	39898	1			T5	1		T51	1		T807	9
valid_sources[0x13]	40636	1			T51	1		T807	4		T499	19
valid_sources[0x14]	40043	1			T66	39		T67	3		T51	1
valid_sources[0x15]	39683	1			T67	1		T51	2		T807	10
valid_sources[0x16]	39512	1			T51	2		T807	12		T499	20
valid_sources[0x17]	40391	1			T67	1		T51	1		T807	7
valid_sources[0x18]	39925	1			T51	1		T807	3		T499	25
valid_sources[0x19]	39904	1			T807	8		T499	19		T364	392
valid_sources[0x1a]	39950	1			T5	3		T258	39		T807	12
valid_sources[0x1b]	40198	1			T67	1		T807	2		T499	32
valid_sources[0x1c]	39971	1			T67	2		T807	6		T499	24
valid_sources[0x1d]	40587	1			T51	1		T807	3		T499	31
valid_sources[0x1e]	40528	1			T51	1		T807	7		T499	19
valid_sources[0x1f]	39367	1			T5	1		T67	1		T807	10
valid_sources[0x20]	40076	1			T51	1		T807	9		T499	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14572257

1

T1

33768

T2

62040

T3

76072

values[0x0]

all_enables

biggest_size

6893422

1

T1

9816

T2

6751

T3

64555

values[0x1]

all_enables

biggest_size

252810

1

T5

20

T66

22

T67

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2875423	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

454044

1

T62

11

T63

79

T64

116

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1125741	1			T62	39		T63	172		T64	260
values[0x0]	1074691	1			T62	8		T63	171		T64	247
values[0x1]	1129035	1			T62	43		T63	159		T64	273

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2226148	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1103319

1

T62

40

T63

177

T64

276

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52941	1			T63	7		T64	28		T191	2
valid_sources[0x01]	51811	1			T62	1		T63	12		T64	2
valid_sources[0x02]	51857	1			T62	1		T63	2		T64	23
valid_sources[0x03]	52672	1			T62	1		T63	4		T64	16
valid_sources[0x04]	51257	1			T62	2		T63	16		T191	3
valid_sources[0x05]	51629	1			T62	1		T63	6		T191	2
valid_sources[0x06]	52612	1			T62	2		T63	4		T64	14
valid_sources[0x07]	51670	1			T62	4		T63	13		T64	18
valid_sources[0x08]	52492	1			T62	1		T63	3		T64	7
valid_sources[0x09]	51583	1			T63	5		T64	7		T191	5
valid_sources[0x0a]	51846	1			T63	12		T192	12		T242	2
valid_sources[0x0b]	51639	1			T62	1		T63	4		T191	2
valid_sources[0x0c]	52065	1			T62	1		T63	34		T191	3
valid_sources[0x0d]	51446	1			T62	1		T63	2		T64	17
valid_sources[0x0e]	52388	1			T62	2		T63	4		T64	1
valid_sources[0x0f]	53356	1			T62	3		T63	1		T64	11
valid_sources[0x10]	52255	1			T62	1		T63	5		T64	21
valid_sources[0x11]	52235	1			T63	16		T64	8		T191	2
valid_sources[0x12]	51661	1			T62	1		T63	5		T64	35
valid_sources[0x13]	52508	1			T63	5		T64	2		T191	3
valid_sources[0x14]	52493	1			T62	1		T63	7		T64	20
valid_sources[0x15]	51316	1			T62	1		T63	9		T191	1
valid_sources[0x16]	52881	1			T62	1		T63	12		T64	33
valid_sources[0x17]	52091	1			T63	4		T64	11		T191	1
valid_sources[0x18]	52060	1			T62	1		T63	4		T191	3
valid_sources[0x19]	51616	1			T63	5		T191	2		T192	15
valid_sources[0x1a]	51992	1			T62	3		T63	1		T191	3
valid_sources[0x1b]	52263	1			T62	3		T63	8		T64	8
valid_sources[0x1c]	52047	1			T62	1		T191	5		T192	2
valid_sources[0x1d]	52231	1			T62	2		T63	5		T64	16
valid_sources[0x1e]	51591	1			T62	3		T63	23		T64	14
valid_sources[0x1f]	52159	1			T62	1		T63	7		T64	12
valid_sources[0x20]	51840	1			T62	1		T63	7		T64	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47788

1

T62

3

T63

9

T64

11

values[0x0]

all_enables

biggest_size

358880

1

T62

5

T63

63

T64

93

values[0x1]

all_enables

biggest_size

47376

1

T62

3

T63

7

T64

12

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3066384	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

498459

1

T62

7

T63

54

T64

98

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1220898	1			T62	41		T63	130		T64	234
values[0x0]	1124321	1			T62	7		T63	139		T64	235
values[0x1]	1219624	1			T62	40		T63	100		T64	246

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2353261	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1211582

1

T62

28

T63

130

T64

227

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56304	1			T62	4		T63	11		T64	12
valid_sources[0x01]	55074	1			T62	1		T63	4		T64	13
valid_sources[0x02]	55306	1			T62	1		T64	19		T191	3
valid_sources[0x03]	54963	1			T63	8		T64	21		T191	2
valid_sources[0x04]	55614	1			T63	4		T64	1		T191	1
valid_sources[0x05]	55347	1			T62	3		T64	8		T191	1
valid_sources[0x06]	54814	1			T62	1		T63	5		T64	19
valid_sources[0x07]	54893	1			T62	2		T63	4		T64	21
valid_sources[0x08]	55953	1			T62	1		T63	12		T64	10
valid_sources[0x09]	56103	1			T62	1		T63	7		T64	11
valid_sources[0x0a]	54944	1			T63	1		T64	26		T191	1
valid_sources[0x0b]	55867	1			T62	4		T63	1		T64	7
valid_sources[0x0c]	56456	1			T62	1		T63	3		T64	9
valid_sources[0x0d]	56584	1			T62	3		T63	18		T64	13
valid_sources[0x0e]	55674	1			T62	2		T63	11		T64	19
valid_sources[0x0f]	56141	1			T62	1		T63	3		T64	7
valid_sources[0x10]	55892	1			T63	1		T64	6		T192	8
valid_sources[0x11]	55801	1			T62	2		T63	6		T64	10
valid_sources[0x12]	55985	1			T62	3		T63	1		T64	14
valid_sources[0x13]	56149	1			T63	1		T64	1		T191	3
valid_sources[0x14]	55198	1			T62	2		T64	10		T191	5
valid_sources[0x15]	56578	1			T63	6		T64	11		T191	1
valid_sources[0x16]	56077	1			T62	3		T63	1		T64	12
valid_sources[0x17]	54888	1			T63	7		T64	8		T191	1
valid_sources[0x18]	55887	1			T62	4		T63	1		T64	12
valid_sources[0x19]	55648	1			T63	10		T64	20		T191	1
valid_sources[0x1a]	55815	1			T62	1		T63	6		T64	16
valid_sources[0x1b]	56073	1			T62	1		T63	7		T64	6
valid_sources[0x1c]	56151	1			T62	2		T63	5		T64	9
valid_sources[0x1d]	56623	1			T63	3		T64	7		T191	1
valid_sources[0x1e]	55228	1			T62	2		T63	4		T64	11
valid_sources[0x1f]	56368	1			T63	3		T64	11		T191	2
valid_sources[0x20]	54711	1			T63	4		T64	3		T191	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52147

1

T62

3

T63

2

T64

8

values[0x0]

all_enables

biggest_size

394032

1

T62

3

T63

50

T64

80

values[0x1]

all_enables

biggest_size

52280

1

T62

1

T63

2

T64

10

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2897456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

456983

1

T62

8

T63

62

T64

110

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1136349	1			T62	33		T63	124		T64	269
values[0x0]	1082775	1			T62	6		T63	142		T64	237
values[0x1]	1135315	1			T62	38		T63	141		T64	276

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2245193	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1109246

1

T62

32

T63

143

T64

280

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53150	1			T62	2		T63	4		T64	5
valid_sources[0x01]	52001	1			T62	1		T63	7		T64	22
valid_sources[0x02]	52576	1			T62	3		T63	4		T64	11
valid_sources[0x03]	52306	1			T64	29		T191	5		T192	13
valid_sources[0x04]	53018	1			T62	1		T63	5		T64	14
valid_sources[0x05]	51906	1			T64	16		T191	3		T192	8
valid_sources[0x06]	52594	1			T62	1		T63	2		T64	18
valid_sources[0x07]	52411	1			T63	7		T64	8		T191	4
valid_sources[0x08]	52151	1			T63	6		T64	15		T191	6
valid_sources[0x09]	53296	1			T62	5		T63	6		T64	18
valid_sources[0x0a]	51993	1			T62	3		T63	7		T64	5
valid_sources[0x0b]	52434	1			T62	3		T63	12		T64	10
valid_sources[0x0c]	53628	1			T62	1		T63	5		T64	13
valid_sources[0x0d]	51751	1			T62	2		T63	5		T64	15
valid_sources[0x0e]	51768	1			T62	2		T63	4		T64	10
valid_sources[0x0f]	53133	1			T62	3		T63	9		T64	23
valid_sources[0x10]	52716	1			T62	2		T63	8		T64	12
valid_sources[0x11]	52086	1			T63	7		T64	7		T191	4
valid_sources[0x12]	52676	1			T64	15		T191	4		T192	6
valid_sources[0x13]	52821	1			T62	1		T63	5		T64	5
valid_sources[0x14]	52722	1			T62	3		T63	7		T64	13
valid_sources[0x15]	51410	1			T63	10		T64	17		T192	6
valid_sources[0x16]	53147	1			T63	7		T64	13		T191	8
valid_sources[0x17]	52306	1			T63	21		T64	6		T191	1
valid_sources[0x18]	52063	1			T62	1		T63	16		T64	8
valid_sources[0x19]	51799	1			T63	8		T64	6		T191	5
valid_sources[0x1a]	52617	1			T62	2		T63	1		T64	17
valid_sources[0x1b]	52676	1			T62	1		T63	3		T64	7
valid_sources[0x1c]	53070	1			T62	2		T63	4		T64	5
valid_sources[0x1d]	53377	1			T63	1		T64	7		T191	3
valid_sources[0x1e]	52921	1			T62	1		T63	8		T64	11
valid_sources[0x1f]	53655	1			T62	1		T63	5		T64	6
valid_sources[0x20]	52439	1			T62	1		T63	7		T64	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47930

1

T62

2

T63

3

T64

10

values[0x0]

all_enables

biggest_size

360980

1

T62

3

T63

55

T64

80

values[0x1]

all_enables

biggest_size

48073

1

T62

3

T63

4

T64

20