Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_26

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_26

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_27

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_28

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_29

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_30

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_31

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_32

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_33

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_34

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_35

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_36

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_37

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_38

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_39

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_40

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_41

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_42

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_43

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_44

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_45

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_47

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_48

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_49

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_50

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_51

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_52

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_53

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_54

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_55

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_56

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_26

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_26

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T27,T28

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_26

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T27,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T25,T27,T28
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_27

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_27

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T27,T28

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_27

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T27,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T25,T27,T28
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_28

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_28

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T27,T28

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_28

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T27,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T25,T27,T28
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_29

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_29

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T27,T28

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_29

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T27,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T25,T27,T28
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_30

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_30

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T27,T28

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_30

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T27,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T25,T27,T28
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_31

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_31

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T27,T28

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_31

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T27,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T25,T27,T28
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_32

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_32

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T204,T299,T300

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_32

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T204,T299,T300
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T204,T299,T300
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_33

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_33

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T204,T299,T300

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_33

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T204,T299,T300
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T204,T299,T300
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_34

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_34

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T305,T330,T353

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_34

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T305,T330,T353
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T305,T330,T353
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_35

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_35

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T305,T330,T353

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_35

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T305,T330,T353
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T305,T330,T353
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_36

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_36

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T208,T209,T318

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_36

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T208,T209,T318
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T208,T209,T318
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_37

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_37

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T208,T209,T318

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_37

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T208,T209,T318
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T208,T209,T318
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_38

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_38

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T12,T35

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_38

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T12,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T34,T12,T35
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_39

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_39

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T12,T35

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_39

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T12,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T34,T12,T35
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_40

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_40

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T12,T35

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_40

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T12,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T34,T12,T35
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_41

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_41

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T34

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_41

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T34
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T11,T34
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_42

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_42

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_42

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_43

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_43

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_43

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_44

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_44

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T98,T180,T181

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_44

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T98,T180,T181
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T98,T180,T181
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_45

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_45

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T15

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_45

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_46

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_46

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T40,T41

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_46

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T39,T40,T41
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T39,T40,T41
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_47

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_47

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T401,T402,T177

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_47

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T401,T402,T177
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T177,T178,T347
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_48

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_48

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T177,T178,T403

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_48

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T177,T178,T403
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T177,T178,T179
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_49

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_49

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T389,T177,T178

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_49

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T389,T177,T178
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T177,T178,T179
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_50

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_50

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T36,T203

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_50

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T36,T203
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T36,T203
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_51

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_51

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T90,T185

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_51

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T90,T185
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T90,T185
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_52

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_52

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T203,T22

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_52

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T203,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T203,T22
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_53

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_53

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T203,T22

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_53

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T203,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T203,T22
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_54

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_54

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T19,T47

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_54

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T19,T47
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T17,T19,T47
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_55

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_55

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T36,T203

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_55

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T36,T203
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T36,T203
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_56

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_56

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T18,T20

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_56

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T16,T18,T20
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_0

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_0

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T177,T178,T179

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_0

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T177,T178,T179
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T177,T178,T179
0	0	Covered	T1,T2,T3