Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312252910	35358726	0	0
DepthKnown_A	312252910	312168882	0	0
RvalidKnown_A	312252910	312168882	0	0
WreadyKnown_A	312252910	312168882	0	0
gen_passthru_fifo.paramCheckPass	846	846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	35358726	0	0
T1	149968	54242	0	0
T2	572665	80677	0	0
T3	510515	80823	0	0
T4	273933	29519	0	0
T33	123646	11192	0	0
T59	128774	22320	0	0
T60	239585	196885	0	0
T98	228885	23663	0	0
T102	108799	183256	0	0
T132	111181	95034	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	312168882	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	312168882	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	312168882	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312252910	27957602	0	0
DepthKnown_A	312252910	312168882	0	0
RvalidKnown_A	312252910	312168882	0	0
WreadyKnown_A	312252910	312168882	0	0
gen_passthru_fifo.paramCheckPass	846	846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	27957602	0	0
T1	149968	50283	0	0
T2	572665	73695	0	0
T3	510515	62658	0	0
T4	273933	23672	0	0
T33	123646	7644	0	0
T59	128774	14693	0	0
T60	239585	97609	0	0
T98	228885	19741	0	0
T102	108799	146553	0	0
T132	111181	91115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	312168882	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	312168882	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	312168882	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312252910	21772527	0	0
DepthKnown_A	312252910	312168882	0	0
RvalidKnown_A	312252910	312168882	0	0
WreadyKnown_A	312252910	312168882	0	0
gen_passthru_fifo.paramCheckPass	846	846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	21772527	0	0
T1	149968	43832	0	0
T2	572665	69621	0	0
T3	510515	144310	0	0
T4	273933	18252	0	0
T33	123646	6294	0	0
T59	128774	6644	0	0
T60	239585	8250	0	0
T98	228885	24317	0	0
T102	108799	302047	0	0
T132	111181	142688	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	312168882	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	312168882	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	312168882	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312252910	21297146	0	0
DepthKnown_A	312252910	312168882	0	0
RvalidKnown_A	312252910	312168882	0	0
WreadyKnown_A	312252910	312168882	0	0
gen_passthru_fifo.paramCheckPass	846	846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	21297146	0	0
T1	149968	43663	0	0
T2	572665	69218	0	0
T3	510515	144059	0	0
T4	273933	17841	0	0
T33	123646	6066	0	0
T59	128774	6370	0	0
T60	239585	6892	0	0
T98	228885	24115	0	0
T102	108799	301627	0	0
T132	111181	142486	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	312168882	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	312168882	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	312168882	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382569513	95108	0	0
DepthKnown_A	382569513	382473543	0	0
RvalidKnown_A	382569513	382473543	0	0
WreadyKnown_A	382569513	382473543	0	0
gen_passthru_fifo.paramCheckPass	2735	2735	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	95108	0	0
T1	149968	29	0	0
T2	572665	38	0	0
T3	510515	18	0	0
T4	273933	49	0	0
T33	123646	27	0	0
T59	128774	26	0	0
T60	239585	27	0	0
T98	228885	53	0	0
T102	108799	145	0	0
T132	111181	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2735	2735	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382569513	97576	0	0
DepthKnown_A	382569513	382473543	0	0
RvalidKnown_A	382569513	382473543	0	0
WreadyKnown_A	382569513	382473543	0	0
gen_passthru_fifo.paramCheckPass	2735	2735	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	97576	0	0
T1	149968	29	0	0
T2	572665	38	0	0
T3	510515	18	0	0
T4	273933	49	0	0
T33	123646	27	0	0
T59	128774	26	0	0
T60	239585	27	0	0
T98	228885	53	0	0
T102	108799	145	0	0
T132	111181	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2735	2735	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382569513	46487	0	0
DepthKnown_A	382569513	382473543	0	0
RvalidKnown_A	382569513	382473543	0	0
WreadyKnown_A	382569513	382473543	0	0
gen_passthru_fifo.paramCheckPass	2735	2735	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	46487	0	0
T1	149968	28	0	0
T2	572665	36	0	0
T3	510515	15	0	0
T4	273933	46	0	0
T33	123646	25	0	0
T59	128774	23	0	0
T60	239585	26	0	0
T98	228885	52	0	0
T102	108799	32	0	0
T132	111181	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2735	2735	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382569513	46487	0	0
DepthKnown_A	382569513	382473543	0	0
RvalidKnown_A	382569513	382473543	0	0
WreadyKnown_A	382569513	382473543	0	0
gen_passthru_fifo.paramCheckPass	2735	2735	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	46487	0	0
T1	149968	28	0	0
T2	572665	36	0	0
T3	510515	15	0	0
T4	273933	46	0	0
T33	123646	25	0	0
T59	128774	23	0	0
T60	239585	26	0	0
T98	228885	52	0	0
T102	108799	32	0	0
T132	111181	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2735	2735	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382569513	48621	0	0
DepthKnown_A	382569513	382473543	0	0
RvalidKnown_A	382569513	382473543	0	0
WreadyKnown_A	382569513	382473543	0	0
gen_passthru_fifo.paramCheckPass	2735	2735	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	48621	0	0
T1	149968	1	0	0
T2	572665	2	0	0
T3	510515	3	0	0
T4	273933	3	0	0
T33	123646	2	0	0
T59	128774	3	0	0
T60	239585	1	0	0
T98	228885	1	0	0
T102	108799	113	0	0
T132	111181	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2735	2735	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382569513	51089	0	0
DepthKnown_A	382569513	382473543	0	0
RvalidKnown_A	382569513	382473543	0	0
WreadyKnown_A	382569513	382473543	0	0
gen_passthru_fifo.paramCheckPass	2735	2735	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	51089	0	0
T1	149968	1	0	0
T2	572665	2	0	0
T3	510515	3	0	0
T4	273933	3	0	0
T33	123646	2	0	0
T59	128774	3	0	0
T60	239585	1	0	0
T98	228885	1	0	0
T102	108799	113	0	0
T132	111181	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382569513	382473543	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2735	2735	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0