Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.80 99.93 99.75 99.51 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 99.80 99.93 99.75 99.51 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL1528152799.93
ALWAYS684375.00
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CONT_ASSIGN1622711100.00
CONT_ASSIGN1624111100.00
CONT_ASSIGN1627511100.00
CONT_ASSIGN1628911100.00
ALWAYS16295199199100.00
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CONT_ASSIGN1732111100.00
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CONT_ASSIGN1732711100.00
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ALWAYS17634199199100.00
ALWAYS17837552552100.00
CONT_ASSIGN1899400
CONT_ASSIGN1900211100.00
CONT_ASSIGN1900311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 0 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16227 1 1
16241 1 1
16275 1 1
16289 1 1
16295 1 1
16296 1 1
16297 1 1
16298 1 1
16299 1 1
16300 1 1
16301 1 1
16302 1 1
16303 1 1
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16305 1 1
16306 1 1
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16308 1 1
16309 1 1
16310 1 1
16311 1 1
16312 1 1
16313 1 1
16314 1 1
16315 1 1
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16317 1 1
16318 1 1
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16327 1 1
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16331 1 1
16332 1 1
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18964 1 1
18968 1 1
18972 1 1
18976 1 1
18980 1 1
18994 unreachable
19002 1 1
19003 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions1983197899.75
Logical1983197899.75
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1648198.96
16482-16500100.00
16500100.00
16500-17002100.00
17005-1762899.73

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 204 203 99.51
TERNARY 16496 2 2 100.00
IF 68 3 2 66.67
CASE 17838 199 199 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16496 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T59
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 17838 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T3,T59
addr_hit[1] Covered T217,T212,T213
addr_hit[2] Covered T217,T212,T213
addr_hit[3] Covered T217,T212,T307
addr_hit[4] Covered T217,T212,T307
addr_hit[5] Covered T217,T212,T213
addr_hit[6] Covered T217,T212,T213
addr_hit[7] Covered T217,T212,T213
addr_hit[8] Covered T217,T212,T213
addr_hit[9] Covered T132,T217,T205
addr_hit[10] Covered T132,T217,T205
addr_hit[11] Covered T132,T217,T205
addr_hit[12] Covered T132,T217,T205
addr_hit[13] Covered T132,T217,T205
addr_hit[14] Covered T132,T217,T205
addr_hit[15] Covered T132,T217,T205
addr_hit[16] Covered T132,T217,T205
addr_hit[17] Covered T98,T217,T180
addr_hit[18] Covered T98,T217,T180
addr_hit[19] Covered T98,T217,T180
addr_hit[20] Covered T98,T217,T180
addr_hit[21] Covered T98,T217,T180
addr_hit[22] Covered T98,T217,T180
addr_hit[23] Covered T98,T217,T180
addr_hit[24] Covered T98,T217,T180
addr_hit[25] Covered T217,T13,T14
addr_hit[26] Covered T217,T13,T14
addr_hit[27] Covered T217,T13,T14
addr_hit[28] Covered T217,T13,T14
addr_hit[29] Covered T217,T13,T14
addr_hit[30] Covered T217,T13,T14
addr_hit[31] Covered T217,T13,T14
addr_hit[32] Covered T217,T13,T14
addr_hit[33] Covered T217,T216,T27
addr_hit[34] Covered T217,T216,T27
addr_hit[35] Covered T217,T216,T27
addr_hit[36] Covered T217,T216,T27
addr_hit[37] Covered T217,T216,T27
addr_hit[38] Covered T217,T216,T27
addr_hit[39] Covered T217,T216,T27
addr_hit[40] Covered T217,T216,T27
addr_hit[41] Covered T217,T216,T27
addr_hit[42] Covered T217,T216,T27
addr_hit[43] Covered T217,T216,T27
addr_hit[44] Covered T217,T216,T27
addr_hit[45] Covered T217,T216,T27
addr_hit[46] Covered T217,T216,T27
addr_hit[47] Covered T217,T216,T27
addr_hit[48] Covered T217,T216,T27
addr_hit[49] Covered T217,T216,T27
addr_hit[50] Covered T217,T216,T27
addr_hit[51] Covered T217,T216,T27
addr_hit[52] Covered T217,T216,T27
addr_hit[53] Covered T217,T216,T27
addr_hit[54] Covered T217,T216,T27
addr_hit[55] Covered T217,T216,T27
addr_hit[56] Covered T217,T216,T27
addr_hit[57] Covered T217,T216,T27
addr_hit[58] Covered T217,T216,T27
addr_hit[59] Covered T217,T216,T27
addr_hit[60] Covered T217,T216,T27
addr_hit[61] Covered T217,T216,T27
addr_hit[62] Covered T217,T216,T27
addr_hit[63] Covered T217,T216,T27
addr_hit[64] Covered T217,T216,T27
addr_hit[65] Covered T217,T10,T216
addr_hit[66] Covered T217,T216,T218
addr_hit[67] Covered T217,T216,T218
addr_hit[68] Covered T217,T10,T216
addr_hit[69] Covered T217,T10,T216
addr_hit[70] Covered T217,T216,T218
addr_hit[71] Covered T217,T216,T218
addr_hit[72] Covered T217,T216,T218
addr_hit[73] Covered T217,T216,T218
addr_hit[74] Covered T217,T216,T218
addr_hit[75] Covered T217,T216,T218
addr_hit[76] Covered T217,T216,T218
addr_hit[77] Covered T217,T216,T218
addr_hit[78] Covered T217,T216,T218
addr_hit[79] Covered T217,T216,T218
addr_hit[80] Covered T217,T216,T218
addr_hit[81] Covered T217,T216,T218
addr_hit[82] Covered T217,T204,T216
addr_hit[83] Covered T217,T204,T216
addr_hit[84] Covered T217,T216,T218
addr_hit[85] Covered T217,T204,T216
addr_hit[86] Covered T217,T204,T216
addr_hit[87] Covered T217,T204,T216
addr_hit[88] Covered T217,T216,T218
addr_hit[89] Covered T217,T216,T218
addr_hit[90] Covered T217,T216,T218
addr_hit[91] Covered T217,T216,T218
addr_hit[92] Covered T217,T216,T218
addr_hit[93] Covered T217,T216,T218
addr_hit[94] Covered T217,T216,T218
addr_hit[95] Covered T217,T216,T218
addr_hit[96] Covered T217,T216,T218
addr_hit[97] Covered T217,T216,T218
addr_hit[98] Covered T217,T216,T218
addr_hit[99] Covered T217,T216,T218
addr_hit[100] Covered T217,T216,T218
addr_hit[101] Covered T217,T216,T218
addr_hit[102] Covered T217,T216,T218
addr_hit[103] Covered T217,T208,T209
addr_hit[104] Covered T217,T208,T209
addr_hit[105] Covered T217,T216,T218
addr_hit[106] Covered T217,T208,T209
addr_hit[107] Covered T217,T208,T209
addr_hit[108] Covered T217,T208,T209
addr_hit[109] Covered T217,T208,T209
addr_hit[110] Covered T217,T208,T209
addr_hit[111] Covered T217,T216,T218
addr_hit[112] Covered T217,T208,T209
addr_hit[113] Covered T217,T216,T218
addr_hit[114] Covered T217,T216,T218
addr_hit[115] Covered T217,T216,T218
addr_hit[116] Covered T217,T216,T218
addr_hit[117] Covered T217,T216,T218
addr_hit[118] Covered T217,T216,T207
addr_hit[119] Covered T217,T216,T207
addr_hit[120] Covered T217,T216,T218
addr_hit[121] Covered T217,T216,T218
addr_hit[122] Covered T217,T216,T218
addr_hit[123] Covered T89,T90,T184
addr_hit[124] Covered T89,T90,T184
addr_hit[125] Covered T89,T90,T184
addr_hit[126] Covered T89,T90,T184
addr_hit[127] Covered T217,T10,T216
addr_hit[128] Covered T217,T10,T216
addr_hit[129] Covered T217,T216,T218
addr_hit[130] Covered T217,T216,T218
addr_hit[131] Covered T217,T216,T218
addr_hit[132] Covered T217,T216,T218
addr_hit[133] Covered T217,T216,T218
addr_hit[134] Covered T217,T216,T218
addr_hit[135] Covered T217,T216,T218
addr_hit[136] Covered T217,T216,T218
addr_hit[137] Covered T217,T216,T218
addr_hit[138] Covered T217,T216,T218
addr_hit[139] Covered T217,T216,T218
addr_hit[140] Covered T217,T216,T218
addr_hit[141] Covered T217,T216,T218
addr_hit[142] Covered T217,T216,T218
addr_hit[143] Covered T217,T216,T218
addr_hit[144] Covered T217,T216,T218
addr_hit[145] Covered T217,T216,T218
addr_hit[146] Covered T217,T216,T218
addr_hit[147] Covered T217,T216,T218
addr_hit[148] Covered T217,T216,T218
addr_hit[149] Covered T59,T112,T312
addr_hit[150] Covered T217,T216,T218
addr_hit[151] Covered T217,T216,T218
addr_hit[152] Covered T89,T90,T184
addr_hit[153] Covered T89,T90,T184
addr_hit[154] Covered T217,T216,T218
addr_hit[155] Covered T217,T216,T218
addr_hit[156] Covered T153,T217,T61
addr_hit[157] Covered T153,T217,T61
addr_hit[158] Covered T153,T217,T61
addr_hit[159] Covered T153,T217,T61
addr_hit[160] Covered T153,T217,T61
addr_hit[161] Covered T217,T216,T218
addr_hit[162] Covered T217,T327,T328
addr_hit[163] Covered T217,T327,T328
addr_hit[164] Covered T217,T216,T218
addr_hit[165] Covered T217,T216,T218
addr_hit[166] Covered T217,T216,T218
addr_hit[167] Covered T217,T216,T218
addr_hit[168] Covered T1,T217,T145
addr_hit[169] Covered T217,T216,T218
addr_hit[170] Covered T217,T216,T218
addr_hit[171] Covered T3,T217,T216
addr_hit[172] Covered T217,T216,T218
addr_hit[173] Covered T217,T216,T218
addr_hit[174] Covered T217,T216,T218
addr_hit[175] Covered T217,T216,T218
addr_hit[176] Covered T217,T216,T218
addr_hit[177] Covered T217,T216,T218
addr_hit[178] Covered T3,T217,T216
addr_hit[179] Covered T217,T216,T218
addr_hit[180] Covered T3,T217,T216
addr_hit[181] Covered T217,T216,T218
addr_hit[182] Covered T67,T499,T500
addr_hit[183] Covered T67,T499,T500
addr_hit[184] Covered T67,T499,T177
addr_hit[185] Covered T67,T499,T500
addr_hit[186] Covered T589,T67,T590
addr_hit[187] Covered T67,T499,T500
addr_hit[188] Covered T98,T132,T217
addr_hit[189] Covered T217,T13,T14
addr_hit[190] Covered T217,T204,T10
addr_hit[191] Covered T89,T90,T184
addr_hit[192] Covered T59,T89,T90
addr_hit[193] Covered T1,T3,T153
addr_hit[194] Covered T1,T3,T59
addr_hit[195] Covered T1,T3,T59
addr_hit[196] Covered T217,T218,T210
addr_hit[197] Covered T73,T67,T124
default Covered T62,T63,T64


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 382569513 244396 0 0
reAfterRv 382569513 244396 0 0
rePulse 382569513 176214 0 0
wePulse 382569513 68182 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 382569513 244396 0 0
T1 149968 12 0 0
T2 572665 0 0 0
T3 510515 3372 0 0
T4 273933 0 0 0
T33 123646 0 0 0
T59 128774 8 0 0
T60 239585 0 0 0
T89 0 44 0 0
T90 0 102 0 0
T98 228885 41 0 0
T102 108799 0 0 0
T132 111181 43 0 0
T184 0 44 0 0
T185 0 104 0 0
T186 0 44 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 382569513 244396 0 0
T1 149968 12 0 0
T2 572665 0 0 0
T3 510515 3372 0 0
T4 273933 0 0 0
T33 123646 0 0 0
T59 128774 8 0 0
T60 239585 0 0 0
T89 0 44 0 0
T90 0 102 0 0
T98 228885 41 0 0
T102 108799 0 0 0
T132 111181 43 0 0
T184 0 44 0 0
T185 0 104 0 0
T186 0 44 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 382569513 176214 0 0
T1 149968 5 0 0
T2 572665 0 0 0
T3 510515 1668 0 0
T4 273933 0 0 0
T33 123646 0 0 0
T59 128774 3 0 0
T60 239585 0 0 0
T89 0 14 0 0
T90 0 31 0 0
T98 228885 16 0 0
T102 108799 0 0 0
T132 111181 17 0 0
T184 0 14 0 0
T185 0 32 0 0
T186 0 14 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 382569513 68182 0 0
T1 149968 7 0 0
T2 572665 0 0 0
T3 510515 1704 0 0
T4 273933 0 0 0
T33 123646 0 0 0
T59 128774 5 0 0
T60 239585 0 0 0
T89 0 30 0 0
T90 0 71 0 0
T98 228885 25 0 0
T102 108799 0 0 0
T132 111181 26 0 0
T184 0 30 0 0
T185 0 72 0 0
T186 0 30 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%