Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_por_aon_n_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T45,T5,T46
0	1	Covered	T45,T5,T46
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T45,T5,T46
1	1	Covered	T45,T5,T46

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	780	716	0	0
selKnown1	1359	523	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	780	716	0	0
T5	2	1	0	0
T25	0	31	0	0
T27	0	3	0	0
T45	2	1	0	0
T46	2	1	0	0
T65	1	0	0	0
T77	29	28	0	0
T78	20	19	0	0
T81	1	0	0	0
T82	1	0	0	0
T95	83	82	0	0
T154	1	0	0	0
T182	0	73	0	0
T183	0	37	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1359	523	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	3	2	0	0
T5	0	1	0	0
T33	2	1	0	0
T45	2	1	0	0
T59	1	0	0	0
T60	1	0	0	0
T89	0	1	0	0
T90	0	4	0	0
T98	1	0	0	0
T102	1	0	0	0
T132	1	0	0	0
T184	0	1	0	0
T185	0	4	0	0
T186	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T45,T5,T46
0	1	Covered	T45,T5,T46
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T45,T5,T46
1	1	Covered	T45,T5,T46

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	780	716	0	0
selKnown1	1359	523	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	780	716	0	0
T5	2	1	0	0
T25	0	31	0	0
T27	0	3	0	0
T45	2	1	0	0
T46	2	1	0	0
T65	1	0	0	0
T77	29	28	0	0
T78	20	19	0	0
T81	1	0	0	0
T82	1	0	0	0
T95	83	82	0	0
T154	1	0	0	0
T182	0	73	0	0
T183	0	37	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1359	523	0	0
T2	2	1	0	0
T3	1	0	0	0
T4	3	2	0	0
T5	0	1	0	0
T33	2	1	0	0
T45	2	1	0	0
T59	1	0	0	0
T60	1	0	0	0
T89	0	1	0	0
T90	0	4	0	0
T98	1	0	0	0
T102	1	0	0	0
T132	1	0	0	0
T184	0	1	0	0
T185	0	4	0	0
T186	0	1	0	0