Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	90.68		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T63,T240,T241	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T62,T64,T242	Yes	T62,T242,T240	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T89,T185,T186	Yes	T89,T185,T186	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T89,T185,T186	Yes	T89,T185,T186	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T66,T51,T62	Yes	T66,T51,T62	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T66,T51,T62	Yes	T66,T51,T62	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T89,T90,T185	Yes	T89,T90,T185	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T33,T4,T45	Yes	T1,T3,T102	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T5,T77,T65	Yes	T5,T77,T65	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T33,T4,T45	Yes	T1,T3,T102	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T33,T4,T45	Yes	T1,T3,T102	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T5,T77,T65	Yes	T5,T77,T65	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T33,T4,T45	Yes	T1,T3,T102	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T5,T77,T65	Yes	T5,T77,T65	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T5,T77,T65	Yes	T5,T77,T65	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T77,T66	Yes	T5,T77,T66	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T5,T77,T65	Yes	T5,T77,T65	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T5,*T77,*T65	Yes	T5,T77,T65	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T5,T77,T65	Yes	T5,T77,T65	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T50,T51,T62	Yes	T50,T51,T62	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T50,T51,T62	Yes	T50,T51,T62	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T50,T51,T62	Yes	T50,T51,T62	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T50,T51,T62	Yes	T50,T51,T62	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T50,T51,T62	Yes	T50,T51,T62	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T50,*T51,T62	Yes	T50,T51,T62	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T62,T63,T191	Yes	T62,T63,T191	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T50,T51,T62	Yes	T50,T51,T62	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T50,T51,T63	Yes	T50,T51,T62	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T50,T51,T62	Yes	T50,T51,T62	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T50,T51,T62	Yes	T50,T51,T62	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T50,T51,T62	Yes	T50,T51,T62	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T50,*T51,T62	Yes	T50,T51,T62	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T50,*T51,*T62	Yes	T50,T51,T62	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T50,T51,T62	Yes	T50,T51,T62	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T65,T67,T50	Yes	T65,T67,T50	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T65,T67,T50	Yes	T65,T67,T50	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T65,T67,T50	Yes	T65,T67,T50	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T65,T67,T50	Yes	T65,T67,T50	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T65,T67,T50	Yes	T65,T67,T50	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T65,*T75,*T76	Yes	T65,T75,T76	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T65,T67,T50	Yes	T65,T67,T50	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T3,T102	Yes	T1,T3,T102	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T3,T102	Yes	T33,T4,T45	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T65,T75,T76	Yes	T65,T75,T76	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T65,T67,T50	Yes	T65,T67,T50	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T3,T102	Yes	T33,T4,T45	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T65,*T75,*T76	Yes	T65,T75,T76	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T102	Yes	T33,T4,T45	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T65,T67,T50	Yes	T65,T67,T50	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T5,T6,T99	Yes	T5,T6,T99	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T73,T50,T124	Yes	T73,T50,T124	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T73,T378,T259	Yes	T73,T378,T259	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T73,T378,T259	Yes	T73,T378,T259	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T73,T50,T124	Yes	T73,T50,T124	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T73,T378,T259	Yes	T73,T378,T259	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T50,*T51,*T62	Yes	T50,T51,T62	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T73,T378,T259	Yes	T73,T378,T259	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T73,T378,T259	Yes	T73,T378,T259	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T378,T259,T379	Yes	T378,T259,T379	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T50,T51,T62	Yes	T73,T50,T124	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T378,T259,T379	Yes	T73,T378,T259	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T50,*T51,T62	Yes	T50,T51,T62	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T259,*T50,*T260	Yes	T378,T259,T379	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T73,T378,T259	Yes	T73,T378,T259	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T89,T184,T186	Yes	T89,T184,T186	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T109,T196,T73	Yes	T109,T196,T73	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T109,T196,T73	Yes	T109,T196,T73	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T109,T196,T73	Yes	T109,T196,T73	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T109,T196,T73	Yes	T109,T196,T73	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T109,T196,T73	Yes	T109,T196,T73	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T109,T196,T73	Yes	T109,T196,T73	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T67,*T62,*T63	Yes	T67,T62,T63	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T109,T196,T73	Yes	T109,T196,T73	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T109,T196,T73	Yes	T109,T196,T73	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T196,T10,T352	Yes	T196,T10,T352	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T109,T196,T10	Yes	T109,T196,T73	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T196,T10,T352	Yes	T196,T10,T352	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T67,*T62,*T63	Yes	T67,T62,T63	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T196,*T10,*T352	Yes	T196,T10,T352	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T109,T196,T73	Yes	T109,T196,T73	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T196,T73,T352	Yes	T196,T73,T352	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T196,T73,T352	Yes	T196,T73,T352	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T196,T73,T352	Yes	T196,T73,T352	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T196,T73,T352	Yes	T196,T73,T352	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T196,T73,T352	Yes	T196,T73,T352	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T196,T73,T352	Yes	T196,T73,T352	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T67,*T62,*T63	Yes	T67,T62,T63	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T196,T73,T352	Yes	T196,T73,T352	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T196,T73,T352	Yes	T196,T73,T352	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T196,T352,T67	Yes	T196,T352,T67	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T196,T352,T359	Yes	T196,T73,T352	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T196,T352,T67	Yes	T196,T352,T67	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T67,*T62,*T63	Yes	T67,T62,T63	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T196,*T352,*T359	Yes	T196,T352,T359	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T196,T73,T352	Yes	T196,T73,T352	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_usbdev_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T18,T196,T20	Yes	T16,T18,T196	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T18,T196	Yes	T18,T196,T20	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T18,T19,T196	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T17,*T18,*T19	Yes	T18,T19,T196	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T33,T4	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T33,T4	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T51,T62,T63	Yes	T51,T62,T63	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T51,T62,T63	Yes	T51,T62,T63	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T51,T62,T63	Yes	T51,T62,T63	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T51,T62,T63	Yes	T51,T62,T63	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T51,T62,T63	Yes	T51,T62,T63	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T51,T62,T63	Yes	T51,T62,T63	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T51,T62,T63	Yes	T51,T62,T63	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T51,T63,T240	Yes	T51,T62,T63	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T51,T62,T63	Yes	T51,T62,T63	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T51,T62,T63	Yes	T51,T62,T63	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T51,T62,T63	Yes	T51,T62,T63	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T51,T62,T63	Yes	T51,T62,T63	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T51,T62,T63	Yes	T51,T62,T63	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T33,T4	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T42,T327,T328	Yes	T42,T327,T328	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T42,T327,T328	Yes	T42,T327,T328	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T42,T327,T328	Yes	T42,T327,T328	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T42,T327,T328	Yes	T42,T327,T328	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T42,T327,T328	Yes	T42,T327,T328	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T327,T328,T329	Yes	T327,T328,T329	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T42,T327,T328	Yes	T42,T327,T328	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T42,T327,T328	Yes	T42,T327,T328	INPUT
tl_hmac_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T42,T327,T328	Yes	T42,T327,T328	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T327,T328	Yes	T42,T327,T328	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T42,T327,T328	Yes	T42,T327,T328	INPUT
tl_hmac_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T42,*T327,*T328	Yes	T42,T327,T328	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T42,T327,T328	Yes	T42,T327,T328	INPUT
tl_kmac_o.d_ready	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T2,T187,T188	Yes	T2,T187,T188	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T60,T187	Yes	T2,T60,T187	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T2,T60,T187	Yes	T2,T60,T187	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T187,T189,T190	Yes	T187,T189,T190	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T2,T60,T187	Yes	T2,T60,T187	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T187,T189,T190	Yes	T187,T189,T190	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T2,T60,T187	Yes	T2,T60,T187	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T2,T60,T187	Yes	T2,T60,T187	INPUT
tl_kmac_i.d_error	Yes	Yes	T62,T64,T191	Yes	T62,T64,T192	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T2,T60,T187	Yes	T2,T60,T187	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T60,T187	Yes	T2,T60,T187	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T2,T60,T187	Yes	T187,T189,T74	INPUT
tl_kmac_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T2,*T60,*T187	Yes	T187,T189,T74	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T2,T60,T187	Yes	T2,T60,T187	INPUT
tl_aes_o.d_ready	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T355,T155,T101	Yes	T355,T155,T101	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T355,T155,T101	Yes	T355,T155,T101	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T355,T155,T101	Yes	T355,T155,T101	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T355,T155,T101	Yes	T355,T155,T101	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T355,T155,T101	Yes	T355,T155,T101	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T355,T155,T101	Yes	T355,T155,T101	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T355,T155,T101	Yes	T355,T155,T101	INPUT
tl_aes_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T355,T155,T101	Yes	T355,T155,T101	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T355,T155,T101	Yes	T355,T155,T101	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T355,T155,T620	Yes	T355,T155,T101	INPUT
tl_aes_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T355,*T155,*T101	Yes	T355,T155,T101	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T355,T155,T101	Yes	T355,T155,T101	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T62,T63,T191	Yes	T62,T63,T191	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T2,T3,T102	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T64,T191	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T2,T3,T102	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T59	Yes	T1,T3,T59	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T59	Yes	T1,T3,T59	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T59	Yes	T1,T3,T59	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T3,T59	Yes	T1,T3,T59	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T3,T59	Yes	T1,T3,T59	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T67,*T62,*T63	Yes	T67,T62,T63	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T3,T59	Yes	T1,T3,T59	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T3,T59	Yes	T1,T3,T59	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T98	Yes	T1,T3,T98	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T59	Yes	T1,T3,T59	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T3,T59	Yes	T1,T3,T59	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T67,*T62,*T63	Yes	T67,T62,T63	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T59	Yes	T1,T3,T59	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T3,T59	Yes	T1,T3,T59	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T102	Yes	T1,T3,T102	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T102	Yes	T1,T3,T102	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T102	Yes	T1,T3,T102	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T1,T3,T102	Yes	T1,T3,T102	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T1,T3,T102	Yes	T1,T3,T102	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T5,*T66,*T258	Yes	T5,T66,T258	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T1,T3,T102	Yes	T1,T3,T102	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T1,T3,T102	Yes	T1,T3,T102	INPUT
tl_otbn_i.d_error	Yes	Yes	T62,T63,T192	Yes	T62,T63,T192	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T102	Yes	T1,T3,T102	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T102	Yes	T1,T3,T102	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T1,T3,T102	Yes	T1,T3,T102	INPUT
tl_otbn_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T5,*T66,*T258	Yes	T5,T66,T258	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T102	Yes	T1,T3,T102	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T1,T3,T102	Yes	T1,T3,T102	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T2,T45,T101	Yes	T2,T45,T101	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T60,T45	Yes	T2,T60,T45	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T2,T60,T45	Yes	T2,T60,T45	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T2,T45,T101	Yes	T2,T45,T101	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T2,T60,T45	Yes	T2,T60,T45	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T2,T60,T45	Yes	T2,T60,T45	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T2,T60,T45	Yes	T2,T60,T45	INPUT
tl_keymgr_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T2,T45,T101	Yes	T2,T45,T101	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T45,T101	Yes	T2,T45,T101	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T2,T45,T101	Yes	T2,T45,T101	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T2,*T45,*T101	Yes	T2,T60,T45	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T2,T60,T45	Yes	T2,T60,T45	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T50,*T51,*T62	Yes	T50,T51,T62	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T50,T51,T62	Yes	T50,T51,T62	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T3,T102,T59	Yes	T3,T102,T59	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T3,T102,T59	Yes	T3,T102,T59	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T50,*T51,*T62	Yes	T50,T51,T62	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T113,T42,T103	Yes	T113,T42,T103	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T113,T42,T103	Yes	T113,T42,T103	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T113,T42,T103	Yes	T113,T42,T103	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T113,T42,T103	Yes	T113,T42,T103	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T113,T42,T103	Yes	T113,T42,T103	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T67,*T62,*T63	Yes	T67,T62,T63	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T113,T42,T103	Yes	T113,T42,T103	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T113,T42,T103	Yes	T113,T42,T103	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T103,T67,T287	Yes	T103,T67,T287	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T113,T103,T114	Yes	T113,T42,T103	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T113,T103,T114	Yes	T113,T42,T103	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T67,*T62,*T63	Yes	T67,T62,T63	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T113,*T103,*T114	Yes	T113,T103,T114	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T113,T42,T103	Yes	T113,T42,T103	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T33,T4	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range