Unified Coverage Report :: Module :: prim_generic_pad

Line Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=3,ScanRole=0 )
Line Coverage for Module self-instances :

SCORE

tb.dut.u_padring.gen_dio_pads[0].u_dio_pad.gen_generic.u_impl_generic

SCORE

tb.dut.u_padring.gen_dio_pads[6].u_dio_pad.gen_generic.u_impl_generic

SCORE

tb.dut.u_padring.gen_dio_pads[7].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	57	0	0
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
51	1	1
57		unreachable
64	1	1
66	1	1
71	1	1

Line Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic

SCORE

tb.dut.u_padring.gen_dio_pads[3].u_dio_pad.gen_generic.u_impl_generic

SCORE

tb.dut.u_padring.gen_dio_pads[4].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

SCORE	LINE
100.00	100.00

tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

Line Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 )
Line Coverage for Module self-instances :

SCORE	LINE
66.67	66.67

tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic

SCORE	LINE
66.67	66.67

tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	2	66.67
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	0	0.00
CONT_ASSIGN	102	0	0
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00

Line No.	Covered	Statements
39		unreachable
51	0	1
102		unreachable
114	1	1
115	1	1

Cond Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 )
Cond Coverage for Module self-instances :

SCORE	COND
66.67	50.00

tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
66.67	50.00

tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	4	2	50.00
Logical	4	2	50.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (((~ie_i)) | attr_i.input_disable)
             ----1----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Unreachable

 LINE       114
 EXPRESSION (ie_n ? 1'bz : inout_io)
             --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

Cond Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=3,ScanRole=0 )
Cond Coverage for Module self-instances :

SCORE

tb.dut.u_padring.gen_dio_pads[0].u_dio_pad.gen_generic.u_impl_generic

SCORE

tb.dut.u_padring.gen_dio_pads[6].u_dio_pad.gen_generic.u_impl_generic

SCORE

tb.dut.u_padring.gen_dio_pads[7].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (((~ie_i)) | attr_i.input_disable)
             ----1----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Unreachable

 LINE       64
 EXPRESSION (ie_n ? 1'bz : inout_io)
             --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       66
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       71
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

Cond Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic

SCORE

tb.dut.u_padring.gen_dio_pads[3].u_dio_pad.gen_generic.u_impl_generic

SCORE

tb.dut.u_padring.gen_dio_pads[4].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

SCORE	COND
100.00	100.00

tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (((~ie_i)) | attr_i.input_disable)
             ----1----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Unreachable

 LINE       78
 EXPRESSION (ie_n ? 1'bz : inout_io)
             --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T30,T31,T32

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T37,T38
1	1	Covered	T18,T7,T20

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T37,T38

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T37,T38
1	1	Covered	T36,T37,T38

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T7,T20

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T10,T8
1	1	Covered	T18,T7,T20

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T10,T8

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T7,T20
1	1	Covered	T7,T10,T8

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T34

Branch Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=3,ScanRole=0 )
Branch Coverage for Module self-instances :

SCORE

tb.dut.u_padring.gen_dio_pads[0].u_dio_pad.gen_generic.u_impl_generic

SCORE

tb.dut.u_padring.gen_dio_pads[6].u_dio_pad.gen_generic.u_impl_generic

SCORE

tb.dut.u_padring.gen_dio_pads[7].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	64	2	2	100.00
TERNARY	71	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	64	(ie_n) ?

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	71	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

Branch Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic

SCORE

tb.dut.u_padring.gen_dio_pads[3].u_dio_pad.gen_generic.u_impl_generic

SCORE

tb.dut.u_padring.gen_dio_pads[4].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
100.00	100.00

tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00



	LineNo.	Expression
-1-:	78	(ie_n) ?

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T18,T7,T20
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T34
0	Covered	T1,T2,T3

Branch Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
66.67	50.00

tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic

SCORE	BRANCH
66.67	50.00

tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	1	50.00
TERNARY	114	2	1	50.00



	LineNo.	Expression
-1-:	114	(ie_n) ?

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

Assert Coverage for Module : prim_generic_pad_wrapper

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	59220	59220	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	59220	59220
T1	70	70
T2	70	70
T3	70	70
T4	70	70
T33	70	70
T59	70	70
T60	70	70
T98	70	70
T102	70	70
T132	70	70

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89	88.89	83.33			83.33	100.00