Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	90.68		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T89,T184,T186	Yes	T89,T184,T186	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T45,T46,T212	Yes	T45,T46,T212	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T45,T46,T212	Yes	T45,T46,T212	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T45,T46,T212	Yes	T45,T46,T212	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T212,T42,T307	Yes	T212,T42,T307	INPUT
tl_uart0_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T212,T213,T216	Yes	T212,T213,T216	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T212,T307,T213	Yes	T212,T42,T307	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T212,T307,T213	Yes	T212,T42,T307	INPUT
tl_uart0_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T212,*T307,*T213	Yes	T212,T307,T213	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T212,T42,T307	Yes	T212,T42,T307	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T132,T205,T206	Yes	T132,T205,T206	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T132,T205,T206	Yes	T132,T205,T206	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T132,T109,T205	Yes	T132,T109,T205	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T132,T109,T205	Yes	T132,T109,T205	INPUT
tl_uart1_i.d_error	Yes	Yes	T63,T64,T191	Yes	T63,T64,T191	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T132,T205,T206	Yes	T132,T205,T206	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T132,T109,T205	Yes	T132,T109,T205	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T132,T109,T205	Yes	T132,T109,T205	INPUT
tl_uart1_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T132,*T205,*T206	Yes	T132,T205,T206	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T132,T109,T205	Yes	T132,T109,T205	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T98,T180,T181	Yes	T98,T180,T181	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T98,T180,T181	Yes	T98,T180,T181	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T98,T180,T181	Yes	T98,T180,T181	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T98,T180,T181	Yes	T98,T180,T181	INPUT
tl_uart2_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T98,T180,T181	Yes	T98,T180,T181	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T98,T180,T181	Yes	T98,T180,T181	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T98,T180,T181	Yes	T98,T180,T181	INPUT
tl_uart2_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T98,*T180,*T181	Yes	T98,T180,T181	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T98,T180,T181	Yes	T98,T180,T181	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
tl_uart3_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
tl_uart3_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T13,*T14,*T15	Yes	T13,T14,T15	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T204,T196,T299	Yes	T204,T196,T299	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T204,T196,T299	Yes	T204,T196,T299	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T204,T109,T196	Yes	T204,T109,T196	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T204,T109,T196	Yes	T204,T109,T196	INPUT
tl_i2c0_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T204,T299,T291	Yes	T204,T299,T291	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T204,T109,T196	Yes	T204,T109,T196	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T204,T109,T196	Yes	T204,T109,T196	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T204,*T196,*T299	Yes	T204,T196,T299	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T204,T109,T196	Yes	T204,T109,T196	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T196,T352,T291	Yes	T196,T352,T291	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T196,T352,T291	Yes	T196,T352,T291	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T109,T196,T73	Yes	T109,T196,T73	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T109,T196,T73	Yes	T109,T196,T73	INPUT
tl_i2c1_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T291,T305,T292	Yes	T291,T305,T292	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T109,T196,T290	Yes	T109,T196,T73	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T109,T196,T290	Yes	T109,T196,T73	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T196,*T352,*T291	Yes	T196,T352,T291	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T109,T196,T73	Yes	T109,T196,T73	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T196,T208,T209	Yes	T196,T208,T209	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T196,T208,T209	Yes	T196,T208,T209	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T109,T196,T208	Yes	T109,T196,T208	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T109,T196,T208	Yes	T109,T196,T208	INPUT
tl_i2c2_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T208,T209,T291	Yes	T208,T209,T291	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T109,T196,T208	Yes	T109,T196,T208	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T109,T196,T208	Yes	T109,T196,T208	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T196,*T208,*T209	Yes	T196,T208,T209	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T109,T196,T208	Yes	T109,T196,T208	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T207,T308,T309	Yes	T207,T308,T309	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T207,T308,T309	Yes	T207,T308,T309	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T73,T207,T308	Yes	T73,T207,T308	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T73,T207,T308	Yes	T73,T207,T308	INPUT
tl_pattgen_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T207,T308,T309	Yes	T207,T308,T309	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T207,T308,T309	Yes	T73,T207,T308	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T207,T308,T309	Yes	T73,T207,T308	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T207,*T308,*T309	Yes	T207,T308,T309	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T73,T207,T308	Yes	T73,T207,T308	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T210,T613,T50	Yes	T210,T613,T50	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T210,T613,T50	Yes	T210,T613,T50	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T73,T210,T613	Yes	T73,T210,T613	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T73,T210,T613	Yes	T73,T210,T613	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T210,T613,T50	Yes	T210,T613,T50	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T210,T613,T50	Yes	T73,T210,T613	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T210,T613,T50	Yes	T73,T210,T613	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T50,*T51,T62	Yes	T50,T51,T62	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T210,*T613,*T50	Yes	T210,T613,T50	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T73,T210,T613	Yes	T73,T210,T613	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T25,T27,T291	Yes	T25,T27,T291	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T25,T27,T291	Yes	T25,T26,T73	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T25,T27,T291	Yes	T25,T26,T73	INPUT
tl_gpio_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T51,*T62,*T63	Yes	T51,T62,T63	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T2,*T33,*T4	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T196,T10,T175	Yes	T196,T10,T175	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T196,T10,T175	Yes	T196,T10,T175	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T196,T73,T10	Yes	T196,T73,T10	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T196,T73,T10	Yes	T196,T73,T10	INPUT
tl_spi_device_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T196,T10,T175	Yes	T196,T10,T175	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T196,T10,T175	Yes	T196,T10,T175	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T196,T73,T10	Yes	T196,T10,T175	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T67,*T62,*T63	Yes	T67,T62,T63	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T196,*T73,*T10	Yes	T196,T10,T175	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T196,T73,T10	Yes	T196,T73,T10	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T243,T624,T210	Yes	T243,T624,T210	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T243,T624,T210	Yes	T243,T624,T210	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T243,T624,T73	Yes	T243,T624,T73	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T243,T624,T73	Yes	T243,T624,T73	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T243,T625,T67	Yes	T243,T625,T67	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T243,T624,T210	Yes	T243,T624,T73	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T243,T624,T210	Yes	T243,T624,T73	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T67,*T62,*T63	Yes	T67,T62,T63	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T243,*T624,*T210	Yes	T243,T624,T210	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T243,T624,T73	Yes	T243,T624,T73	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T59,T4,T90	Yes	T59,T4,T90	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T59,T4,T90	Yes	T59,T4,T90	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T59,T4,T90	Yes	T59,T4,T90	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T59,T4,T90	Yes	T59,T4,T90	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T59,T4,T90	Yes	T59,T4,T90	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T4,T90	Yes	T59,T4,T90	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T59,T4,T90	Yes	T59,T4,T90	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T50,*T51,*T62	Yes	T50,T51,T62	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T59,*T4,*T90	Yes	T59,T4,T90	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T59,T4,T90	Yes	T59,T4,T90	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T62,T63,T191	Yes	T62,T63,T191	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T50,*T51,*T62	Yes	T50,T51,T62	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T98,T132,T45	Yes	T98,T132,T45	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T102,T98,T132	Yes	T102,T98,T132	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T98,T132,T355	Yes	T98,T132,T355	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T98,T33	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T2,T98,T33	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T98,*T132,*T45	Yes	T98,T132,T45	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T50,*T51,*T62	Yes	T50,T51,T62	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T2,*T60,*T101	Yes	T2,T60,T101	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T3,T102	Yes	T1,T3,T102	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T3,T102	Yes	T33,T4,T45	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T3,T102	Yes	T33,T4,T45	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T102	Yes	T33,T4,T45	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T60,T61,T13	Yes	T60,T61,T13	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T60,T61,T13	Yes	T60,T61,T13	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T60,T61,T13	Yes	T60,T61,T13	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T60,T61,T13	Yes	T60,T61,T13	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T42,T68,T65	Yes	T60,T61,T69	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T70,T71,T72	Yes	T73,T70,T71	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T69,T42,T74	Yes	T60,T61,T13	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T65,*T75,*T76	Yes	T65,T75,T76	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T69,*T74,*T65	Yes	T60,T61,T13	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T60,T61,T13	Yes	T60,T61,T13	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T17,T156,T19	Yes	T17,T156,T19	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T156,T19	Yes	T17,T156,T19	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T67,*T62,*T63	Yes	T67,T62,T63	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T2,*T33,*T4	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T59,*T45,*T89	Yes	T59,T45,T89	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T113,T42,T114	Yes	T113,T42,T114	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T113,T42,T114	Yes	T113,T42,T114	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T113,T42,T114	Yes	T113,T42,T114	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T113,T42,T114	Yes	T113,T42,T114	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T113,T114,T115	Yes	T113,T114,T115	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T113,T114,T115	Yes	T113,T42,T114	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T113,T114,T115	Yes	T113,T42,T114	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T67,*T62,*T63	Yes	T67,T62,T63	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T113,*T114,*T115	Yes	T113,T114,T115	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T113,T42,T114	Yes	T113,T42,T114	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T2,T59,T33	Yes	T2,T59,T33	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T33,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T2,T59,T33	Yes	T2,T59,T33	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T59,T33	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T2,T59,T33	Yes	T2,T59,T33	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T5,*T66,*T258	Yes	T5,T66,T258	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T59,T89,T90	Yes	T59,T89,T90	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T59,T89,T90	Yes	T59,T89,T90	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T59,T89,T90	Yes	T59,T89,T90	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T59,T89,T90	Yes	T59,T89,T90	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T59,T89,T90	Yes	T59,T89,T90	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T89,T90	Yes	T59,T89,T90	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T59,T89,T90	Yes	T59,T89,T90	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T59,*T89,*T90	Yes	T59,T89,T90	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T59,T89,T90	Yes	T59,T89,T90	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T90,T185	Yes	T4,T90,T185	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T90,T185	Yes	T4,T90,T185	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T4,T90,T185	Yes	T4,T90,T185	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T4,T90,T185	Yes	T4,T90,T185	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T62,T64,T191	Yes	T62,T63,T64	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T90,T185	Yes	T4,T90,T185	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T90,T185	Yes	T4,T90,T185	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T4,T90,T185	Yes	T4,T90,T185	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T67,*T62,*T63	Yes	T67,T62,T63	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T4,*T90,*T185	Yes	T4,T90,T185	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T4,T90,T185	Yes	T4,T90,T185	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T17,*T19,*T47	Yes	T17,T19,T47	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T5,*T65,*T66	Yes	T5,T65,T66	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range