Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T117,T283,T50
0	1	Covered	T117,T283,T284
1	0	Covered	T50

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T117,T283,T50
1	Covered	T117,T283,T50

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T117,T283,T50
1	Covered	T117,T283,T50

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T117,T283,T284
1	1	Covered	T117,T283,T50

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T117,T283,T50
1	0	Covered	T117,T283,T50
1	1	Covered	T117,T283,T284

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T117,T283,T50

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T117,T283,T50
0	Covered	T117,T283,T50

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T117,T283,T50
0	Covered	T117,T283,T50

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	624505820	606745566	0	0
CheckNGreaterZero_A	1692	1692	0	0
GntImpliesReady_A	624505820	5367	0	0
GntImpliesValid_A	624505820	5367	0	0
GrantKnown_A	624505820	606745566	0	0
IdxKnown_A	624505820	606745566	0	0
IndexIsCorrect_A	624505820	5367	0	0
NoReadyValidNoGrant_A	624505820	0	0	0
Priority_A	624505820	5367	0	0
ReadyAndValidImplyGrant_A	624505820	5367	0	0
ReqAndReadyImplyGrant_A	624505820	5367	0	0
ReqImpliesValid_A	624505820	5367	0	0
ValidKnown_A	624505820	606745566	0	0
gen_data_port_assertion.DataFlow_A	624505820	5367	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624505820	606745566	0	0
T1	299936	299926	0	0
T2	1145330	1145104	0	0
T3	1021030	1020914	0	0
T4	547866	547530	0	0
T33	247292	246538	0	0
T59	257548	257424	0	0
T60	479170	479054	0	0
T98	457770	457668	0	0
T102	217598	217586	0	0
T132	222362	222352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692	1692	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T33	2	2	0	0
T59	2	2	0	0
T60	2	2	0	0
T98	2	2	0	0
T102	2	2	0	0
T132	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624505820	5367	0	0
T47	299968	0	0	0
T117	176088	1788	0	0
T190	155004	0	0	0
T219	490232	0	0	0
T243	180284	0	0	0
T283	0	1790	0	0
T284	0	1789	0	0
T328	207654	0	0	0
T329	144688	0	0	0
T371	685632	0	0	0
T372	150914	0	0	0
T373	315576	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624505820	5367	0	0
T47	299968	0	0	0
T117	176088	1788	0	0
T190	155004	0	0	0
T219	490232	0	0	0
T243	180284	0	0	0
T283	0	1790	0	0
T284	0	1789	0	0
T328	207654	0	0	0
T329	144688	0	0	0
T371	685632	0	0	0
T372	150914	0	0	0
T373	315576	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624505820	606745566	0	0
T1	299936	299926	0	0
T2	1145330	1145104	0	0
T3	1021030	1020914	0	0
T4	547866	547530	0	0
T33	247292	246538	0	0
T59	257548	257424	0	0
T60	479170	479054	0	0
T98	457770	457668	0	0
T102	217598	217586	0	0
T132	222362	222352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624505820	606745566	0	0
T1	299936	299926	0	0
T2	1145330	1145104	0	0
T3	1021030	1020914	0	0
T4	547866	547530	0	0
T33	247292	246538	0	0
T59	257548	257424	0	0
T60	479170	479054	0	0
T98	457770	457668	0	0
T102	217598	217586	0	0
T132	222362	222352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624505820	5367	0	0
T47	299968	0	0	0
T117	176088	1788	0	0
T190	155004	0	0	0
T219	490232	0	0	0
T243	180284	0	0	0
T283	0	1790	0	0
T284	0	1789	0	0
T328	207654	0	0	0
T329	144688	0	0	0
T371	685632	0	0	0
T372	150914	0	0	0
T373	315576	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624505820	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624505820	5367	0	0
T47	299968	0	0	0
T117	176088	1788	0	0
T190	155004	0	0	0
T219	490232	0	0	0
T243	180284	0	0	0
T283	0	1790	0	0
T284	0	1789	0	0
T328	207654	0	0	0
T329	144688	0	0	0
T371	685632	0	0	0
T372	150914	0	0	0
T373	315576	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624505820	5367	0	0
T47	299968	0	0	0
T117	176088	1788	0	0
T190	155004	0	0	0
T219	490232	0	0	0
T243	180284	0	0	0
T283	0	1790	0	0
T284	0	1789	0	0
T328	207654	0	0	0
T329	144688	0	0	0
T371	685632	0	0	0
T372	150914	0	0	0
T373	315576	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624505820	5367	0	0
T47	299968	0	0	0
T117	176088	1788	0	0
T190	155004	0	0	0
T219	490232	0	0	0
T243	180284	0	0	0
T283	0	1790	0	0
T284	0	1789	0	0
T328	207654	0	0	0
T329	144688	0	0	0
T371	685632	0	0	0
T372	150914	0	0	0
T373	315576	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624505820	5367	0	0
T47	299968	0	0	0
T117	176088	1788	0	0
T190	155004	0	0	0
T219	490232	0	0	0
T243	180284	0	0	0
T283	0	1790	0	0
T284	0	1789	0	0
T328	207654	0	0	0
T329	144688	0	0	0
T371	685632	0	0	0
T372	150914	0	0	0
T373	315576	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624505820	606745566	0	0
T1	299936	299926	0	0
T2	1145330	1145104	0	0
T3	1021030	1020914	0	0
T4	547866	547530	0	0
T33	247292	246538	0	0
T59	257548	257424	0	0
T60	479170	479054	0	0
T98	457770	457668	0	0
T102	217598	217586	0	0
T132	222362	222352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624505820	5367	0	0
T47	299968	0	0	0
T117	176088	1788	0	0
T190	155004	0	0	0
T219	490232	0	0	0
T243	180284	0	0	0
T283	0	1790	0	0
T284	0	1789	0	0
T328	207654	0	0	0
T329	144688	0	0	0
T371	685632	0	0	0
T372	150914	0	0	0
T373	315576	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T117,T283,T50
0	1	Covered	T117,T283,T284
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T117,T283,T284
1	Covered	T117,T283,T50

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T117,T283,T284
1	Covered	T117,T283,T50

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T117,T283,T284
1	1	Covered	T117,T283,T284

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T117,T283,T50
1	0	Covered	T117,T283,T284
1	1	Covered	T117,T283,T284

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T117,T283,T284

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T117,T283,T50
0	Covered	T117,T283,T284

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T117,T283,T50
0	Covered	T117,T283,T284

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	312252910	303372783	0	0
CheckNGreaterZero_A	846	846	0	0
GntImpliesReady_A	312252910	4377	0	0
GntImpliesValid_A	312252910	4377	0	0
GrantKnown_A	312252910	303372783	0	0
IdxKnown_A	312252910	303372783	0	0
IndexIsCorrect_A	312252910	4377	0	0
NoReadyValidNoGrant_A	312252910	0	0	0
Priority_A	312252910	4377	0	0
ReadyAndValidImplyGrant_A	312252910	4377	0	0
ReqAndReadyImplyGrant_A	312252910	4377	0	0
ReqImpliesValid_A	312252910	4377	0	0
ValidKnown_A	312252910	303372783	0	0
gen_data_port_assertion.DataFlow_A	312252910	4377	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	303372783	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	4377	0	0
T47	149984	0	0	0
T117	88044	1458	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	1460	0	0
T284	0	1459	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	4377	0	0
T47	149984	0	0	0
T117	88044	1458	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	1460	0	0
T284	0	1459	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	303372783	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	303372783	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	4377	0	0
T47	149984	0	0	0
T117	88044	1458	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	1460	0	0
T284	0	1459	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	4377	0	0
T47	149984	0	0	0
T117	88044	1458	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	1460	0	0
T284	0	1459	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	4377	0	0
T47	149984	0	0	0
T117	88044	1458	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	1460	0	0
T284	0	1459	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	4377	0	0
T47	149984	0	0	0
T117	88044	1458	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	1460	0	0
T284	0	1459	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	4377	0	0
T47	149984	0	0	0
T117	88044	1458	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	1460	0	0
T284	0	1459	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	303372783	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	4377	0	0
T47	149984	0	0	0
T117	88044	1458	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	1460	0	0
T284	0	1459	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T117,T283,T50
0	1	Covered	T117,T283,T284
1	0	Covered	T50

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T117,T283,T50
1	Covered	T117,T283,T50

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T117,T283,T50
1	Covered	T117,T283,T50

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T117,T283,T284
1	1	Covered	T117,T283,T50

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T117,T283,T50
1	0	Covered	T117,T283,T50
1	1	Covered	T117,T283,T284

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T117,T283,T50

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T117,T283,T50
0	Covered	T117,T283,T50

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T117,T283,T50
0	Covered	T117,T283,T50

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	312252910	303372783	0	0
CheckNGreaterZero_A	846	846	0	0
GntImpliesReady_A	312252910	990	0	0
GntImpliesValid_A	312252910	990	0	0
GrantKnown_A	312252910	303372783	0	0
IdxKnown_A	312252910	303372783	0	0
IndexIsCorrect_A	312252910	990	0	0
NoReadyValidNoGrant_A	312252910	0	0	0
Priority_A	312252910	990	0	0
ReadyAndValidImplyGrant_A	312252910	990	0	0
ReqAndReadyImplyGrant_A	312252910	990	0	0
ReqImpliesValid_A	312252910	990	0	0
ValidKnown_A	312252910	303372783	0	0
gen_data_port_assertion.DataFlow_A	312252910	990	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	303372783	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	990	0	0
T47	149984	0	0	0
T117	88044	330	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	330	0	0
T284	0	330	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	990	0	0
T47	149984	0	0	0
T117	88044	330	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	330	0	0
T284	0	330	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	303372783	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	303372783	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	990	0	0
T47	149984	0	0	0
T117	88044	330	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	330	0	0
T284	0	330	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	990	0	0
T47	149984	0	0	0
T117	88044	330	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	330	0	0
T284	0	330	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	990	0	0
T47	149984	0	0	0
T117	88044	330	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	330	0	0
T284	0	330	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	990	0	0
T47	149984	0	0	0
T117	88044	330	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	330	0	0
T284	0	330	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	990	0	0
T47	149984	0	0	0
T117	88044	330	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	330	0	0
T284	0	330	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	303372783	0	0
T1	149968	149963	0	0
T2	572665	572552	0	0
T3	510515	510457	0	0
T4	273933	273765	0	0
T33	123646	123269	0	0
T59	128774	128712	0	0
T60	239585	239527	0	0
T98	228885	228834	0	0
T102	108799	108793	0	0
T132	111181	111176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	990	0	0
T47	149984	0	0	0
T117	88044	330	0	0
T190	77502	0	0	0
T219	245116	0	0	0
T243	90142	0	0	0
T283	0	330	0	0
T284	0	330	0	0
T328	103827	0	0	0
T329	72344	0	0	0
T371	342816	0	0	0
T372	75457	0	0	0
T373	157788	0	0	0