SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.83 | 99.34 | 100.00 | 100.00 | 100.00 | u_pinmux_strap_sampling |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 846 | 846 | 0 | 0 |
OutputsKnown_A | 79105125 | 78588696 | 0 | 0 |
gen_no_flops.OutputDelay_A | 79105125 | 78588696 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 846 | 846 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T59 | 1 | 1 | 0 | 0 |
T60 | 1 | 1 | 0 | 0 |
T98 | 1 | 1 | 0 | 0 |
T102 | 1 | 1 | 0 | 0 |
T132 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 79105125 | 78588696 | 0 | 0 |
T1 | 360918 | 360315 | 0 | 0 |
T2 | 138831 | 138194 | 0 | 0 |
T3 | 123248 | 122898 | 0 | 0 |
T4 | 77312 | 76527 | 0 | 0 |
T33 | 31017 | 30422 | 0 | 0 |
T59 | 35586 | 35273 | 0 | 0 |
T60 | 58452 | 57871 | 0 | 0 |
T98 | 56087 | 55304 | 0 | 0 |
T102 | 415253 | 414485 | 0 | 0 |
T132 | 267617 | 267221 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 79105125 | 78588696 | 0 | 0 |
T1 | 360918 | 360315 | 0 | 0 |
T2 | 138831 | 138194 | 0 | 0 |
T3 | 123248 | 122898 | 0 | 0 |
T4 | 77312 | 76527 | 0 | 0 |
T33 | 31017 | 30422 | 0 | 0 |
T59 | 35586 | 35273 | 0 | 0 |
T60 | 58452 | 57871 | 0 | 0 |
T98 | 56087 | 55304 | 0 | 0 |
T102 | 415253 | 414485 | 0 | 0 |
T132 | 267617 | 267221 | 0 | 0 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 846 | 846 | 0 | 0 |
OutputsKnown_A | 79105125 | 78588696 | 0 | 0 |
gen_no_flops.OutputDelay_A | 79105125 | 78588696 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 846 | 846 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T59 | 1 | 1 | 0 | 0 |
T60 | 1 | 1 | 0 | 0 |
T98 | 1 | 1 | 0 | 0 |
T102 | 1 | 1 | 0 | 0 |
T132 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 79105125 | 78588696 | 0 | 0 |
T1 | 360918 | 360315 | 0 | 0 |
T2 | 138831 | 138194 | 0 | 0 |
T3 | 123248 | 122898 | 0 | 0 |
T4 | 77312 | 76527 | 0 | 0 |
T33 | 31017 | 30422 | 0 | 0 |
T59 | 35586 | 35273 | 0 | 0 |
T60 | 58452 | 57871 | 0 | 0 |
T98 | 56087 | 55304 | 0 | 0 |
T102 | 415253 | 414485 | 0 | 0 |
T132 | 267617 | 267221 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 79105125 | 78588696 | 0 | 0 |
T1 | 360918 | 360315 | 0 | 0 |
T2 | 138831 | 138194 | 0 | 0 |
T3 | 123248 | 122898 | 0 | 0 |
T4 | 77312 | 76527 | 0 | 0 |
T33 | 31017 | 30422 | 0 | 0 |
T59 | 35586 | 35273 | 0 | 0 |
T60 | 58452 | 57871 | 0 | 0 |
T98 | 56087 | 55304 | 0 | 0 |
T102 | 415253 | 414485 | 0 | 0 |
T132 | 267617 | 267221 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |