Unified Coverage Report :: Module :: chip_earlgrey_asic

Module : chip_earlgrey_asic

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.90	80.00	100.00	95.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	92.83	80.00	100.00	98.48

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.83	80.00	100.00	98.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.90	95.60	94.48	91.84		95.40	97.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
top_earlgrey	94.67	95.54	94.06	91.74		95.22	96.81
u_ast	92.94			92.94
u_padring	99.08	99.40	99.80	96.57		99.60	100.00
u_prim_usb_diff_rx	96.30	100.00	88.89			100.00

Line Coverage for Module : chip_earlgrey_asic

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	786	1	0	0.00
CONT_ASSIGN	797	1	0	0.00
CONT_ASSIGN	822	1	0	0.00
CONT_ASSIGN	829	1	0	0.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	847	1	1	100.00
CONT_ASSIGN	851	1	0	0.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	1018	1	1	100.00
CONT_ASSIGN	1019	1	1	100.00
CONT_ASSIGN	1020	1	1	100.00
CONT_ASSIGN	1021	1	1	100.00
CONT_ASSIGN	1028	1	1	100.00
CONT_ASSIGN	1045	1	1	100.00
CONT_ASSIGN	1046	1	1	100.00
CONT_ASSIGN	1047	1	1	100.00
CONT_ASSIGN	1048	1	1	100.00
CONT_ASSIGN	1052	1	1	100.00
CONT_ASSIGN	1053	1	1	100.00
CONT_ASSIGN	1054	1	1	100.00
CONT_ASSIGN	1055	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
212	1	1
213	1	1
786	0	1
797	0	1
822	0	1
829	0	1
836	1	1
839	1	1
845	1	1
847	1	1
851	0	1
854	1	1
1018	1	1
1019	1	1
1020	1	1
1021	1	1
1028	1	1
1045	1	1
1046	1	1
1047	1	1
1048	1	1
1052	1	1
1053	1	1
1054	1	1
1055	1	1

---

Cond Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T59,T4,T90

---

Toggle Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Totals	70	64	91.43
Total Bits	140	134	95.71
Total Bits 0->1	70	70	100.00
Total Bits 1->0	70	64	91.43

Ports	70	64	91.43
Port Bits	140	134	95.71
Port Bits 0->1	70	70	100.00
Port Bits 1->0	70	64	91.43

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
POR_N	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INOUT
USB_P	Yes	Yes	T16,T18,T7	Yes	T18,T20,T129	INOUT
USB_N	Yes	Yes	T18,T20,T129	Yes	T18,T7,T20	INOUT
CC1	No	No		Yes	T7,T8,T9	INOUT
CC2	No	No		Yes	T7,T8,T9	INOUT
FLASH_TEST_VOLT	No	No		Yes	T7,T8,T9	INOUT
FLASH_TEST_MODE0	No	No		Yes	T7,T8,T9	INOUT
FLASH_TEST_MODE1	No	No		Yes	T7,T8,T9	INOUT
OTP_EXT_VOLT	No	No		Yes	T7,T8,T9	INOUT
SPI_HOST_D0	Yes	Yes	T10,T11,T12	Yes	T7,T10,T8	INOUT
SPI_HOST_D1	Yes	Yes	T10,T11,T12	Yes	T7,T10,T11	INOUT
SPI_HOST_D2	Yes	Yes	T11,T197,T198	Yes	T7,T11,T197	INOUT
SPI_HOST_D3	Yes	Yes	T11,T197,T198	Yes	T7,T11,T197	INOUT
SPI_HOST_CLK	Yes	Yes	T10,T11,T12	Yes	T10,T8,T11	INOUT
SPI_HOST_CS_L	Yes	Yes	T10,T67,T11	Yes	T7,T10,T8	INOUT
SPI_DEV_D0	Yes	Yes	T10,T175,T176	Yes	T10,T175,T176	INOUT
SPI_DEV_D1	Yes	Yes	T10,T175,T176	Yes	T10,T175,T176	INOUT
SPI_DEV_D2	Yes	Yes	T11,T197,T198	Yes	T11,T197,T198	INOUT
SPI_DEV_D3	Yes	Yes	T11,T197,T198	Yes	T8,T11,T197	INOUT
SPI_DEV_CLK	Yes	Yes	T10,T175,T176	Yes	T7,T10,T175	INOUT
SPI_DEV_CS_L	Yes	Yes	T7,T10,T175	Yes	T7,T10,T175	INOUT
IOR8	Yes	Yes	T21,T7,T203	Yes	T21,T7,T203	INOUT
IOR9	Yes	Yes	T21,T7,T22	Yes	T21,T7,T36	INOUT
IOA0	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INOUT
IOA1	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INOUT
IOA2	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INOUT
IOA3	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INOUT
IOA4	Yes	Yes	T98,T180,T181	Yes	T98,T180,T181	INOUT
IOA5	Yes	Yes	T98,T180,T181	Yes	T98,T180,T181	INOUT
IOA6	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INOUT
IOA7	Yes	Yes	T204,T25,T26	Yes	T204,T25,T7	INOUT
IOA8	Yes	Yes	T204,T25,T26	Yes	T204,T25,T7	INOUT
IOB0	Yes	Yes	T34,T35,T30	Yes	T8,T34,T35	INOUT
IOB1	Yes	Yes	T34,T35,T30	Yes	T7,T34,T35	INOUT
IOB2	Yes	Yes	T30,T31,T32	Yes	T8,T30,T31	INOUT
IOB3	Yes	Yes	T21,T203,T22	Yes	T21,T7,T203	INOUT
IOB4	Yes	Yes	T132,T205,T206	Yes	T132,T205,T206	INOUT
IOB5	Yes	Yes	T132,T205,T206	Yes	T132,T205,T206	INOUT
IOB6	Yes	Yes	T21,T25,T203	Yes	T21,T25,T7	INOUT
IOB7	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	INOUT
IOB8	Yes	Yes	T21,T25,T203	Yes	T25,T203,T141	INOUT
IOB9	Yes	Yes	T21,T25,T22	Yes	T25,T27,T207	INOUT
IOB10	Yes	Yes	T25,T27,T207	Yes	T25,T27,T207	INOUT
IOB11	Yes	Yes	T25,T208,T209	Yes	T25,T7,T208	INOUT
IOB12	Yes	Yes	T25,T208,T209	Yes	T25,T7,T208	INOUT
IOC0	Yes	Yes	T42,T175,T176	Yes	T175,T176,T8	INOUT
IOC1	Yes	Yes	T175,T176,T211	Yes	T175,T176,T8	INOUT
IOC2	Yes	Yes	T175,T176,T211	Yes	T175,T176,T211	INOUT
IOC3	Yes	Yes	T212,T213,T7	Yes	T212,T213,T314	INOUT
IOC4	Yes	Yes	T212,T213,T7	Yes	T212,T213,T314	INOUT
IOC5	Yes	Yes	T95,T77,T78	Yes	T95,T77,T78	INOUT
IOC6	Yes	Yes	T13,T81,T82	Yes	T13,T81,T82	INOUT
IOC7	Yes	Yes	T18,T21,T203	Yes	T16,T18,T21	INOUT
IOC8	Yes	Yes	T95,T77,T78	Yes	T95,T77,T78	INOUT
IOC9	Yes	Yes	T21,T25,T36	Yes	T21,T25,T36	INOUT
IOC10	Yes	Yes	T25,T27,T210	Yes	T25,T7,T27	INOUT
IOC11	Yes	Yes	T25,T27,T210	Yes	T25,T7,T27	INOUT
IOC12	Yes	Yes	T25,T27,T210	Yes	T25,T7,T27	INOUT
IOR0	Yes	Yes	T45,T5,T46	Yes	T45,T5,T46	INOUT
IOR1	Yes	Yes	T45,T5,T46	Yes	T45,T5,T46	INOUT
IOR2	Yes	Yes	T45,T5,T46	Yes	T45,T5,T46	INOUT
IOR3	Yes	Yes	T45,T5,T46	Yes	T45,T5,T46	INOUT
IOR4	Yes	Yes	T45,T5,T46	Yes	T45,T5,T46	INOUT
IOR5	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	INOUT
IOR6	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	INOUT
IOR7	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	INOUT
IOR10	Yes	Yes	T25,T27,T28	Yes	T25,T27,T8	INOUT
IOR11	Yes	Yes	T25,T27,T28	Yes	T25,T27,T8	INOUT
IOR12	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	INOUT
IOR13	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	INOUT

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	786	1	0	0.00
CONT_ASSIGN	797	1	0	0.00
CONT_ASSIGN	822	1	0	0.00
CONT_ASSIGN	829	1	0	0.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	847	1	1	100.00
CONT_ASSIGN	851	1	0	0.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	1018	1	1	100.00
CONT_ASSIGN	1019	1	1	100.00
CONT_ASSIGN	1020	1	1	100.00
CONT_ASSIGN	1021	1	1	100.00
CONT_ASSIGN	1028	1	1	100.00
CONT_ASSIGN	1045	1	1	100.00
CONT_ASSIGN	1046	1	1	100.00
CONT_ASSIGN	1047	1	1	100.00
CONT_ASSIGN	1048	1	1	100.00
CONT_ASSIGN	1052	1	1	100.00
CONT_ASSIGN	1053	1	1	100.00
CONT_ASSIGN	1054	1	1	100.00
CONT_ASSIGN	1055	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
212	1	1
213	1	1
786	0	1
797	0	1
822	0	1
829	0	1
836	1	1
839	1	1
845	1	1
847	1	1
851	0	1
854	1	1
1018	1	1
1019	1	1
1020	1	1
1021	1	1
1028	1	1
1045	1	1
1046	1	1
1047	1	1
1048	1	1
1052	1	1
1053	1	1
1054	1	1
1055	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T59,T4,T90

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	66	64	96.97
Total Bits	132	130	98.48
Total Bits 0->1	66	66	100.00
Total Bits 1->0	66	64	96.97

Ports	66	64	96.97
Port Bits	132	130	98.48
Port Bits 0->1	66	66	100.00
Port Bits 1->0	66	64	96.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
POR_N	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INOUT
USB_P	Yes	Yes	T16,T18,T7	Yes	T18,T20,T129	INOUT
USB_N	Yes	Yes	T18,T20,T129	Yes	T18,T7,T20	INOUT
CC1	No	No		Yes	T7,T8,T9	INOUT
CC2	No	No		Yes	T7,T8,T9	INOUT
FLASH_TEST_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0	Yes	Yes	T10,T11,T12	Yes	T7,T10,T8	INOUT
SPI_HOST_D1	Yes	Yes	T10,T11,T12	Yes	T7,T10,T11	INOUT
SPI_HOST_D2	Yes	Yes	T11,T197,T198	Yes	T7,T11,T197	INOUT
SPI_HOST_D3	Yes	Yes	T11,T197,T198	Yes	T7,T11,T197	INOUT
SPI_HOST_CLK	Yes	Yes	T10,T11,T12	Yes	T10,T8,T11	INOUT
SPI_HOST_CS_L	Yes	Yes	T10,T67,T11	Yes	T7,T10,T8	INOUT
SPI_DEV_D0	Yes	Yes	T10,T175,T176	Yes	T10,T175,T176	INOUT
SPI_DEV_D1	Yes	Yes	T10,T175,T176	Yes	T10,T175,T176	INOUT
SPI_DEV_D2	Yes	Yes	T11,T197,T198	Yes	T11,T197,T198	INOUT
SPI_DEV_D3	Yes	Yes	T11,T197,T198	Yes	T8,T11,T197	INOUT
SPI_DEV_CLK	Yes	Yes	T10,T175,T176	Yes	T7,T10,T175	INOUT
SPI_DEV_CS_L	Yes	Yes	T7,T10,T175	Yes	T7,T10,T175	INOUT
IOR8	Yes	Yes	T21,T7,T203	Yes	T21,T7,T203	INOUT
IOR9	Yes	Yes	T21,T7,T22	Yes	T21,T7,T36	INOUT
IOA0	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INOUT
IOA1	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INOUT
IOA2	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INOUT
IOA3	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INOUT
IOA4	Yes	Yes	T98,T180,T181	Yes	T98,T180,T181	INOUT
IOA5	Yes	Yes	T98,T180,T181	Yes	T98,T180,T181	INOUT
IOA6	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INOUT
IOA7	Yes	Yes	T204,T25,T26	Yes	T204,T25,T7	INOUT
IOA8	Yes	Yes	T204,T25,T26	Yes	T204,T25,T7	INOUT
IOB0	Yes	Yes	T34,T35,T30	Yes	T8,T34,T35	INOUT
IOB1	Yes	Yes	T34,T35,T30	Yes	T7,T34,T35	INOUT
IOB2	Yes	Yes	T30,T31,T32	Yes	T8,T30,T31	INOUT
IOB3	Yes	Yes	T21,T203,T22	Yes	T21,T7,T203	INOUT
IOB4	Yes	Yes	T132,T205,T206	Yes	T132,T205,T206	INOUT
IOB5	Yes	Yes	T132,T205,T206	Yes	T132,T205,T206	INOUT
IOB6	Yes	Yes	T21,T25,T203	Yes	T21,T25,T7	INOUT
IOB7	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	INOUT
IOB8	Yes	Yes	T21,T25,T203	Yes	T25,T203,T141	INOUT
IOB9	Yes	Yes	T21,T25,T22	Yes	T25,T27,T207	INOUT
IOB10	Yes	Yes	T25,T27,T207	Yes	T25,T27,T207	INOUT
IOB11	Yes	Yes	T25,T208,T209	Yes	T25,T7,T208	INOUT
IOB12	Yes	Yes	T25,T208,T209	Yes	T25,T7,T208	INOUT
IOC0	Yes	Yes	T42,T175,T176	Yes	T175,T176,T8	INOUT
IOC1	Yes	Yes	T175,T176,T211	Yes	T175,T176,T8	INOUT
IOC2	Yes	Yes	T175,T176,T211	Yes	T175,T176,T211	INOUT
IOC3	Yes	Yes	T212,T213,T7	Yes	T212,T213,T314	INOUT
IOC4	Yes	Yes	T212,T213,T7	Yes	T212,T213,T314	INOUT
IOC5	Yes	Yes	T95,T77,T78	Yes	T95,T77,T78	INOUT
IOC6	Yes	Yes	T13,T81,T82	Yes	T13,T81,T82	INOUT
IOC7	Yes	Yes	T18,T21,T203	Yes	T16,T18,T21	INOUT
IOC8	Yes	Yes	T95,T77,T78	Yes	T95,T77,T78	INOUT
IOC9	Yes	Yes	T21,T25,T36	Yes	T21,T25,T36	INOUT
IOC10	Yes	Yes	T25,T27,T210	Yes	T25,T7,T27	INOUT
IOC11	Yes	Yes	T25,T27,T210	Yes	T25,T7,T27	INOUT
IOC12	Yes	Yes	T25,T27,T210	Yes	T25,T7,T27	INOUT
IOR0	Yes	Yes	T45,T5,T46	Yes	T45,T5,T46	INOUT
IOR1	Yes	Yes	T45,T5,T46	Yes	T45,T5,T46	INOUT
IOR2	Yes	Yes	T45,T5,T46	Yes	T45,T5,T46	INOUT
IOR3	Yes	Yes	T45,T5,T46	Yes	T45,T5,T46	INOUT
IOR4	Yes	Yes	T45,T5,T46	Yes	T45,T5,T46	INOUT
IOR5	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	INOUT
IOR6	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	INOUT
IOR7	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	INOUT
IOR10	Yes	Yes	T25,T27,T28	Yes	T25,T27,T8	INOUT
IOR11	Yes	Yes	T25,T27,T28	Yes	T25,T27,T8	INOUT
IOR12	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	INOUT
IOR13	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	INOUT