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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.67 95.60 94.48 91.84 95.40 97.20 99.53


Total test records in report: 2735
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T647 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2036732264 May 16 04:29:31 PM PDT 24 May 16 04:35:49 PM PDT 24 3796039532 ps
T644 /workspace/coverage/default/49.chip_sw_all_escalation_resets.3775056133 May 16 04:33:05 PM PDT 24 May 16 04:42:31 PM PDT 24 4586881388 ps
T853 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.968900121 May 16 04:05:34 PM PDT 24 May 16 04:10:46 PM PDT 24 3184176673 ps
T321 /workspace/coverage/default/9.chip_sw_all_escalation_resets.1433897666 May 16 04:34:06 PM PDT 24 May 16 04:44:01 PM PDT 24 6197545220 ps
T854 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1053949925 May 16 04:23:22 PM PDT 24 May 16 04:36:14 PM PDT 24 6732461800 ps
T855 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1161483904 May 16 04:09:19 PM PDT 24 May 16 04:21:47 PM PDT 24 6283690714 ps
T856 /workspace/coverage/default/2.chip_sw_edn_sw_mode.1322608095 May 16 04:26:57 PM PDT 24 May 16 04:44:41 PM PDT 24 6811922020 ps
T632 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.4017712719 May 16 04:28:47 PM PDT 24 May 16 04:36:50 PM PDT 24 3332747400 ps
T857 /workspace/coverage/default/2.chip_sw_aes_entropy.1029949879 May 16 04:25:51 PM PDT 24 May 16 04:29:40 PM PDT 24 2802295288 ps
T858 /workspace/coverage/default/1.chip_sw_aes_smoketest.810174157 May 16 04:21:12 PM PDT 24 May 16 04:26:23 PM PDT 24 3211658684 ps
T94 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3235622504 May 16 04:02:12 PM PDT 24 May 16 04:11:11 PM PDT 24 4720543672 ps
T92 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3076408017 May 16 04:03:51 PM PDT 24 May 16 04:27:35 PM PDT 24 6772204848 ps
T680 /workspace/coverage/default/3.chip_sw_all_escalation_resets.3343718865 May 16 04:25:48 PM PDT 24 May 16 04:36:41 PM PDT 24 4645662052 ps
T704 /workspace/coverage/default/45.chip_sw_all_escalation_resets.1006525470 May 16 04:30:15 PM PDT 24 May 16 04:41:03 PM PDT 24 4437650598 ps
T352 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2592860037 May 16 04:03:29 PM PDT 24 May 16 04:06:31 PM PDT 24 2643313400 ps
T600 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1238223540 May 16 04:26:30 PM PDT 24 May 16 04:36:34 PM PDT 24 6284461561 ps
T24 /workspace/coverage/default/0.chip_sw_usbdev_config_host.1332212332 May 16 04:02:44 PM PDT 24 May 16 04:37:13 PM PDT 24 7476166080 ps
T859 /workspace/coverage/default/0.chip_sw_kmac_smoketest.597264996 May 16 04:09:32 PM PDT 24 May 16 04:15:02 PM PDT 24 2714898392 ps
T142 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3829445418 May 16 04:13:15 PM PDT 24 May 16 04:35:52 PM PDT 24 16565810972 ps
T860 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.627077400 May 16 04:26:06 PM PDT 24 May 16 04:34:45 PM PDT 24 3438159640 ps
T861 /workspace/coverage/default/2.chip_sw_edn_kat.1580438231 May 16 04:26:06 PM PDT 24 May 16 04:36:19 PM PDT 24 2981703946 ps
T218 /workspace/coverage/default/2.chip_sw_plic_sw_irq.1360387623 May 16 04:24:59 PM PDT 24 May 16 04:30:26 PM PDT 24 2915591536 ps
T233 /workspace/coverage/default/37.chip_sw_all_escalation_resets.2704886723 May 16 04:33:57 PM PDT 24 May 16 04:42:33 PM PDT 24 4985149026 ps
T250 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3612164289 May 16 04:25:20 PM PDT 24 May 16 04:32:21 PM PDT 24 5447792830 ps
T251 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.4017712369 May 16 04:13:10 PM PDT 24 May 16 04:21:29 PM PDT 24 4413541456 ps
T252 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3881698610 May 16 04:26:17 PM PDT 24 May 16 05:26:26 PM PDT 24 24748294345 ps
T253 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.4077832429 May 16 04:03:41 PM PDT 24 May 16 04:08:25 PM PDT 24 3092330666 ps
T254 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.463060777 May 16 04:06:19 PM PDT 24 May 16 04:16:59 PM PDT 24 4702016268 ps
T255 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.823596502 May 16 04:30:56 PM PDT 24 May 16 04:36:22 PM PDT 24 3925608780 ps
T256 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3422907740 May 16 04:31:42 PM PDT 24 May 16 04:38:28 PM PDT 24 4281409656 ps
T66 /workspace/coverage/default/1.chip_jtag_mem_access.388263488 May 16 04:06:04 PM PDT 24 May 16 04:31:18 PM PDT 24 13577857998 ps
T257 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2868918838 May 16 04:30:19 PM PDT 24 May 16 04:36:25 PM PDT 24 3083795310 ps
T862 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1148661405 May 16 04:33:26 PM PDT 24 May 16 04:40:46 PM PDT 24 3902301074 ps
T49 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2321462941 May 16 04:23:39 PM PDT 24 May 16 04:31:46 PM PDT 24 4123116080 ps
T863 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3331865200 May 16 04:06:13 PM PDT 24 May 16 04:20:07 PM PDT 24 9622012374 ps
T864 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.653901218 May 16 04:24:13 PM PDT 24 May 16 04:36:29 PM PDT 24 7570395854 ps
T583 /workspace/coverage/default/2.chip_sw_aes_masking_off.2097501588 May 16 04:26:04 PM PDT 24 May 16 04:30:46 PM PDT 24 2311074268 ps
T359 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1826939864 May 16 04:24:47 PM PDT 24 May 16 04:44:43 PM PDT 24 11828920330 ps
T865 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3413234863 May 16 04:06:52 PM PDT 24 May 16 04:16:00 PM PDT 24 4763200552 ps
T349 /workspace/coverage/default/0.chip_sw_edn_boot_mode.696818119 May 16 04:09:38 PM PDT 24 May 16 04:18:41 PM PDT 24 3223044766 ps
T172 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2456718101 May 16 04:05:00 PM PDT 24 May 16 04:12:00 PM PDT 24 7490448314 ps
T626 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.927573822 May 16 04:30:58 PM PDT 24 May 16 04:37:02 PM PDT 24 3551625784 ps
T866 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3301947576 May 16 04:26:40 PM PDT 24 May 16 04:34:26 PM PDT 24 5108782600 ps
T234 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1099425534 May 16 04:03:19 PM PDT 24 May 16 04:18:05 PM PDT 24 7486765288 ps
T867 /workspace/coverage/default/1.chip_sw_kmac_smoketest.637702476 May 16 04:22:49 PM PDT 24 May 16 04:27:42 PM PDT 24 2422859680 ps
T713 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2329726583 May 16 04:28:25 PM PDT 24 May 16 04:34:59 PM PDT 24 3851030512 ps
T478 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.390055253 May 16 04:04:31 PM PDT 24 May 16 04:38:35 PM PDT 24 13312351178 ps
T868 /workspace/coverage/default/1.chip_sw_uart_smoketest.3225531622 May 16 04:22:46 PM PDT 24 May 16 04:27:40 PM PDT 24 2743662080 ps
T582 /workspace/coverage/default/5.chip_sw_all_escalation_resets.4277919738 May 16 04:32:50 PM PDT 24 May 16 04:42:03 PM PDT 24 4089233794 ps
T869 /workspace/coverage/default/2.chip_sw_csrng_smoketest.2986787220 May 16 04:25:36 PM PDT 24 May 16 04:29:53 PM PDT 24 2664456814 ps
T259 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2543097916 May 16 04:11:38 PM PDT 24 May 16 04:19:53 PM PDT 24 8957759595 ps
T336 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2860988899 May 16 04:02:50 PM PDT 24 May 16 04:06:28 PM PDT 24 2580688750 ps
T297 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1393081023 May 16 04:23:42 PM PDT 24 May 16 04:33:14 PM PDT 24 3933686642 ps
T333 /workspace/coverage/default/55.chip_sw_all_escalation_resets.1067220577 May 16 04:28:16 PM PDT 24 May 16 04:41:02 PM PDT 24 4953896204 ps
T682 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2031465403 May 16 04:32:19 PM PDT 24 May 16 04:40:38 PM PDT 24 4238082760 ps
T870 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2407937129 May 16 04:04:54 PM PDT 24 May 16 04:15:28 PM PDT 24 4098301252 ps
T871 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2647840788 May 16 04:09:36 PM PDT 24 May 16 04:14:18 PM PDT 24 3090155208 ps
T332 /workspace/coverage/default/26.chip_sw_all_escalation_resets.4182775304 May 16 04:28:47 PM PDT 24 May 16 04:37:15 PM PDT 24 4781614328 ps
T872 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.4055641518 May 16 04:04:30 PM PDT 24 May 16 04:16:24 PM PDT 24 8374208000 ps
T873 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.33093418 May 16 04:27:29 PM PDT 24 May 16 04:31:34 PM PDT 24 3086806226 ps
T874 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1423665163 May 16 04:15:43 PM PDT 24 May 16 04:19:19 PM PDT 24 2555549536 ps
T173 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2543547703 May 16 04:11:57 PM PDT 24 May 16 04:17:05 PM PDT 24 2717156762 ps
T875 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1028105092 May 16 04:12:31 PM PDT 24 May 16 04:20:39 PM PDT 24 5057086936 ps
T876 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.485387623 May 16 04:23:07 PM PDT 24 May 16 04:59:56 PM PDT 24 21203517153 ps
T877 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3278169139 May 16 04:08:20 PM PDT 24 May 16 04:16:29 PM PDT 24 3977991400 ps
T685 /workspace/coverage/default/13.chip_sw_all_escalation_resets.1388383417 May 16 04:29:11 PM PDT 24 May 16 04:42:40 PM PDT 24 4593290868 ps
T640 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3311189227 May 16 04:32:53 PM PDT 24 May 16 04:38:16 PM PDT 24 3934196032 ps
T119 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.452424838 May 16 04:23:49 PM PDT 24 May 16 04:28:02 PM PDT 24 2608740578 ps
T878 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.531402236 May 16 04:13:28 PM PDT 24 May 16 04:20:57 PM PDT 24 3695800014 ps
T8 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1105627862 May 16 04:24:24 PM PDT 24 May 16 04:29:32 PM PDT 24 3446243030 ps
T226 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1624960137 May 16 04:13:22 PM PDT 24 May 16 05:00:42 PM PDT 24 10223217768 ps
T337 /workspace/coverage/default/1.chip_sw_hmac_enc.507611707 May 16 04:10:14 PM PDT 24 May 16 04:13:53 PM PDT 24 3235254504 ps
T298 /workspace/coverage/default/1.chip_sival_flash_info_access.2153674558 May 16 04:09:19 PM PDT 24 May 16 04:14:01 PM PDT 24 3051885998 ps
T379 /workspace/coverage/default/1.chip_sw_kmac_app_rom.242087561 May 16 04:11:36 PM PDT 24 May 16 04:15:20 PM PDT 24 2954870968 ps
T879 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3114365342 May 16 04:05:45 PM PDT 24 May 16 04:13:26 PM PDT 24 5026765180 ps
T115 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2737019675 May 16 04:24:53 PM PDT 24 May 16 04:37:57 PM PDT 24 6968577084 ps
T283 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1605916351 May 16 04:06:03 PM PDT 24 May 16 04:11:03 PM PDT 24 2863389700 ps
T880 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3076271902 May 16 04:26:34 PM PDT 24 May 16 04:30:56 PM PDT 24 2679932664 ps
T650 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3113871369 May 16 04:28:19 PM PDT 24 May 16 04:34:44 PM PDT 24 3620801080 ps
T195 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1372503793 May 16 04:25:10 PM PDT 24 May 16 04:40:20 PM PDT 24 6877155908 ps
T881 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3243824652 May 16 04:04:52 PM PDT 24 May 16 04:31:36 PM PDT 24 9921437712 ps
T229 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.4052771252 May 16 04:26:26 PM PDT 24 May 16 04:56:33 PM PDT 24 22679704714 ps
T882 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3551996405 May 16 04:02:00 PM PDT 24 May 16 04:23:12 PM PDT 24 5802925848 ps
T883 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1428526943 May 16 04:24:11 PM PDT 24 May 16 04:41:00 PM PDT 24 5674753760 ps
T661 /workspace/coverage/default/6.chip_sw_all_escalation_resets.4000248794 May 16 04:28:33 PM PDT 24 May 16 04:44:00 PM PDT 24 5292399652 ps
T210 /workspace/coverage/default/0.chip_sw_power_sleep_load.1234678178 May 16 04:04:13 PM PDT 24 May 16 04:10:21 PM PDT 24 4440921150 ps
T694 /workspace/coverage/default/99.chip_sw_all_escalation_resets.1591204752 May 16 04:33:18 PM PDT 24 May 16 04:41:55 PM PDT 24 3991206888 ps
T625 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3825721585 May 16 04:08:49 PM PDT 24 May 16 04:15:35 PM PDT 24 3892192830 ps
T884 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.679197785 May 16 04:26:13 PM PDT 24 May 16 05:12:52 PM PDT 24 12972312803 ps
T308 /workspace/coverage/default/1.chip_sw_pattgen_ios.326541217 May 16 04:09:03 PM PDT 24 May 16 04:12:49 PM PDT 24 2134630060 ps
T885 /workspace/coverage/default/12.chip_sw_all_escalation_resets.4272123378 May 16 04:28:14 PM PDT 24 May 16 04:36:24 PM PDT 24 5205481398 ps
T270 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.848086560 May 16 04:10:15 PM PDT 24 May 16 04:24:37 PM PDT 24 5368164520 ps
T314 /workspace/coverage/default/0.chip_sw_uart_tx_rx.2915856350 May 16 04:03:04 PM PDT 24 May 16 04:13:05 PM PDT 24 3817983730 ps
T637 /workspace/coverage/default/1.chip_sw_all_escalation_resets.4169891231 May 16 04:07:02 PM PDT 24 May 16 04:15:31 PM PDT 24 4345178084 ps
T886 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2716363317 May 16 04:05:30 PM PDT 24 May 16 04:15:51 PM PDT 24 4949040760 ps
T681 /workspace/coverage/default/77.chip_sw_all_escalation_resets.1094908999 May 16 04:33:16 PM PDT 24 May 16 04:43:46 PM PDT 24 5037751400 ps
T84 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3338367155 May 16 04:03:15 PM PDT 24 May 16 04:31:42 PM PDT 24 12656124726 ps
T887 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1135126634 May 16 04:04:04 PM PDT 24 May 16 04:27:09 PM PDT 24 8138771710 ps
T888 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3277974731 May 16 04:26:41 PM PDT 24 May 16 04:33:42 PM PDT 24 7937313964 ps
T67 /workspace/coverage/default/2.chip_jtag_csr_rw.2109852422 May 16 04:15:44 PM PDT 24 May 16 04:36:38 PM PDT 24 12081511033 ps
T143 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2024307824 May 16 04:08:32 PM PDT 24 May 16 04:16:56 PM PDT 24 7656158590 ps
T889 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1567763741 May 16 04:25:09 PM PDT 24 May 16 04:29:45 PM PDT 24 3179354810 ps
T613 /workspace/coverage/default/1.chip_sw_power_idle_load.803186983 May 16 04:17:08 PM PDT 24 May 16 04:26:17 PM PDT 24 4438387632 ps
T340 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3696709263 May 16 04:31:15 PM PDT 24 May 16 04:37:29 PM PDT 24 4085428400 ps
T683 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.567329596 May 16 04:32:32 PM PDT 24 May 16 04:39:34 PM PDT 24 4037895946 ps
T890 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2143698859 May 16 04:09:57 PM PDT 24 May 16 04:17:01 PM PDT 24 3751289928 ps
T11 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.269274505 May 16 04:06:37 PM PDT 24 May 16 04:18:39 PM PDT 24 6700036387 ps
T127 /workspace/coverage/default/2.chip_tap_straps_testunlock0.3890608976 May 16 04:24:35 PM PDT 24 May 16 04:37:09 PM PDT 24 8593189519 ps
T128 /workspace/coverage/default/4.chip_tap_straps_rma.312165433 May 16 04:27:27 PM PDT 24 May 16 04:36:47 PM PDT 24 6760354970 ps
T891 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3843176343 May 16 04:12:40 PM PDT 24 May 16 04:17:22 PM PDT 24 3071658162 ps
T50 /workspace/coverage/default/1.chip_jtag_csr_rw.2929812798 May 16 04:06:35 PM PDT 24 May 16 04:32:35 PM PDT 24 11912509268 ps
T382 /workspace/coverage/default/4.chip_tap_straps_testunlock0.1437854136 May 16 04:24:53 PM PDT 24 May 16 04:30:59 PM PDT 24 4449679946 ps
T383 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.775276717 May 16 04:30:38 PM PDT 24 May 16 04:36:39 PM PDT 24 4087749748 ps
T384 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3620472652 May 16 04:06:12 PM PDT 24 May 16 04:11:07 PM PDT 24 3080787133 ps
T271 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2922875290 May 16 04:25:01 PM PDT 24 May 16 04:36:29 PM PDT 24 4373229359 ps
T385 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3332544235 May 16 04:30:31 PM PDT 24 May 16 04:35:44 PM PDT 24 3530274802 ps
T386 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2626658672 May 16 04:13:11 PM PDT 24 May 16 04:21:27 PM PDT 24 4255529880 ps
T309 /workspace/coverage/default/0.chip_sw_pattgen_ios.1337317891 May 16 04:03:40 PM PDT 24 May 16 04:07:15 PM PDT 24 2118402770 ps
T152 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2000283498 May 16 04:17:46 PM PDT 24 May 16 04:44:44 PM PDT 24 11057574834 ps
T387 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1336804200 May 16 04:04:58 PM PDT 24 May 16 04:58:44 PM PDT 24 18170975093 ps
T892 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1779442812 May 16 04:29:28 PM PDT 24 May 16 04:34:47 PM PDT 24 3847596504 ps
T893 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1904511932 May 16 04:23:08 PM PDT 24 May 16 04:28:42 PM PDT 24 3930259510 ps
T894 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.4240639344 May 16 04:28:21 PM PDT 24 May 16 04:40:29 PM PDT 24 3846764936 ps
T641 /workspace/coverage/default/44.chip_sw_all_escalation_resets.3612838332 May 16 04:29:00 PM PDT 24 May 16 04:38:27 PM PDT 24 4580775768 ps
T211 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.674733050 May 16 04:24:15 PM PDT 24 May 16 07:29:42 PM PDT 24 65126576820 ps
T895 /workspace/coverage/default/1.chip_sw_edn_sw_mode.680447644 May 16 04:13:18 PM PDT 24 May 16 04:36:55 PM PDT 24 7132908004 ps
T628 /workspace/coverage/default/63.chip_sw_all_escalation_resets.1707521493 May 16 04:37:47 PM PDT 24 May 16 04:48:20 PM PDT 24 4616414800 ps
T85 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3094516658 May 16 04:23:08 PM PDT 24 May 16 04:36:56 PM PDT 24 9087340298 ps
T896 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2124058075 May 16 04:15:02 PM PDT 24 May 16 04:19:54 PM PDT 24 2610130850 ps
T70 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3192342746 May 16 04:05:38 PM PDT 24 May 16 04:19:53 PM PDT 24 7570372125 ps
T897 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2977198238 May 16 04:25:34 PM PDT 24 May 16 04:32:37 PM PDT 24 3431609420 ps
T898 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3457904376 May 16 04:12:04 PM PDT 24 May 16 04:30:41 PM PDT 24 10544816924 ps
T376 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2317735393 May 16 04:06:34 PM PDT 24 May 16 04:12:16 PM PDT 24 3678415257 ps
T161 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1560307039 May 16 04:06:07 PM PDT 24 May 16 04:17:06 PM PDT 24 6695281530 ps
T899 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2068031072 May 16 04:25:27 PM PDT 24 May 16 04:31:25 PM PDT 24 5962199376 ps
T272 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2867251876 May 16 04:24:16 PM PDT 24 May 16 04:32:05 PM PDT 24 3221492750 ps
T900 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3771331717 May 16 04:10:16 PM PDT 24 May 16 04:47:03 PM PDT 24 9970669064 ps
T475 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.81301637 May 16 04:23:49 PM PDT 24 May 16 04:36:50 PM PDT 24 4614592900 ps
T901 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1625542463 May 16 04:08:02 PM PDT 24 May 16 04:17:57 PM PDT 24 4303752120 ps
T902 /workspace/coverage/default/0.chip_sw_aes_masking_off.2441428370 May 16 04:05:49 PM PDT 24 May 16 04:11:04 PM PDT 24 3014240712 ps
T903 /workspace/coverage/default/2.chip_tap_straps_rma.2395920608 May 16 04:24:51 PM PDT 24 May 16 04:35:50 PM PDT 24 6934886614 ps
T657 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2905552518 May 16 04:28:41 PM PDT 24 May 16 04:34:42 PM PDT 24 3913066600 ps
T904 /workspace/coverage/default/1.chip_sw_flash_crash_alert.3324512315 May 16 04:15:06 PM PDT 24 May 16 04:26:30 PM PDT 24 5180472744 ps
T905 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1881477440 May 16 04:09:10 PM PDT 24 May 16 04:16:47 PM PDT 24 3539054767 ps
T106 /workspace/coverage/default/0.chip_plic_all_irqs_10.3513219471 May 16 04:08:22 PM PDT 24 May 16 04:17:41 PM PDT 24 3198333586 ps
T906 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1033544698 May 16 04:03:47 PM PDT 24 May 16 04:07:52 PM PDT 24 2868814436 ps
T907 /workspace/coverage/default/0.chip_sival_flash_info_access.3171525927 May 16 04:02:17 PM PDT 24 May 16 04:08:17 PM PDT 24 2537314188 ps
T262 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.891951200 May 16 04:26:46 PM PDT 24 May 16 04:37:54 PM PDT 24 4592078712 ps
T908 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3925329208 May 16 04:02:28 PM PDT 24 May 16 04:33:35 PM PDT 24 8500273349 ps
T909 /workspace/coverage/default/2.chip_sw_aon_timer_irq.3321943074 May 16 04:23:18 PM PDT 24 May 16 04:30:45 PM PDT 24 3892483324 ps
T260 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.177275727 May 16 04:04:47 PM PDT 24 May 16 04:14:16 PM PDT 24 9079048388 ps
T322 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.163921052 May 16 04:21:31 PM PDT 24 May 16 04:27:25 PM PDT 24 18761082918 ps
T910 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1412111302 May 16 04:24:28 PM PDT 24 May 16 04:27:31 PM PDT 24 2533142564 ps
T911 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2302435298 May 16 04:08:12 PM PDT 24 May 16 04:14:28 PM PDT 24 3136508244 ps
T912 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3651404180 May 16 04:07:37 PM PDT 24 May 16 04:27:37 PM PDT 24 9572450499 ps
T913 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3743031189 May 16 04:23:16 PM PDT 24 May 16 04:42:40 PM PDT 24 8520085206 ps
T914 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1686675180 May 16 04:06:33 PM PDT 24 May 16 04:24:55 PM PDT 24 7528743443 ps
T315 /workspace/coverage/default/1.chip_sw_uart_tx_rx.913499041 May 16 04:09:13 PM PDT 24 May 16 04:18:07 PM PDT 24 3932934362 ps
T915 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2960585085 May 16 04:08:46 PM PDT 24 May 16 04:16:30 PM PDT 24 4541938322 ps
T916 /workspace/coverage/default/0.chip_sw_csrng_smoketest.3691324405 May 16 04:09:32 PM PDT 24 May 16 04:13:03 PM PDT 24 2362884812 ps
T34 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1856444266 May 16 04:07:51 PM PDT 24 May 16 04:13:01 PM PDT 24 2675294678 ps
T917 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1807854530 May 16 04:16:05 PM PDT 24 May 16 04:18:31 PM PDT 24 1902993142 ps
T273 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3017800017 May 16 04:05:56 PM PDT 24 May 16 04:17:48 PM PDT 24 5473939816 ps
T225 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1494228921 May 16 04:04:57 PM PDT 24 May 16 04:32:09 PM PDT 24 8151243300 ps
T918 /workspace/coverage/default/0.chip_sw_edn_kat.1589727749 May 16 04:05:38 PM PDT 24 May 16 04:15:47 PM PDT 24 3389451170 ps
T919 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.501202087 May 16 04:24:26 PM PDT 24 May 16 04:36:21 PM PDT 24 4651212520 ps
T71 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.241204614 May 16 04:10:16 PM PDT 24 May 16 04:24:58 PM PDT 24 6676606531 ps
T291 /workspace/coverage/default/1.chip_plic_all_irqs_0.704247709 May 16 04:12:22 PM PDT 24 May 16 04:34:42 PM PDT 24 6427638510 ps
T920 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1808590455 May 16 04:04:43 PM PDT 24 May 16 04:20:16 PM PDT 24 5738294391 ps
T921 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3152617156 May 16 04:13:16 PM PDT 24 May 16 04:23:38 PM PDT 24 5406008472 ps
T922 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1754327124 May 16 04:24:39 PM PDT 24 May 16 04:32:57 PM PDT 24 5061203018 ps
T923 /workspace/coverage/default/1.chip_sw_example_rom.1312132971 May 16 04:06:26 PM PDT 24 May 16 04:08:19 PM PDT 24 2355552406 ps
T924 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.652334787 May 16 04:06:45 PM PDT 24 May 16 04:20:49 PM PDT 24 8182437704 ps
T925 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.104054054 May 16 04:26:53 PM PDT 24 May 16 04:32:31 PM PDT 24 2996004238 ps
T926 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2623668610 May 16 04:22:26 PM PDT 24 May 16 04:26:44 PM PDT 24 2899532389 ps
T927 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2569060243 May 16 04:04:15 PM PDT 24 May 16 04:16:00 PM PDT 24 5202841348 ps
T928 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.4056823625 May 16 04:23:33 PM PDT 24 May 16 04:34:35 PM PDT 24 5678554720 ps
T929 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3026862645 May 16 04:25:00 PM PDT 24 May 16 04:32:56 PM PDT 24 3379964808 ps
T930 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2904345505 May 16 04:28:03 PM PDT 24 May 16 04:53:54 PM PDT 24 8730335151 ps
T931 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2925016827 May 16 04:22:05 PM PDT 24 May 16 04:44:07 PM PDT 24 7757455730 ps
T932 /workspace/coverage/default/3.chip_tap_straps_testunlock0.981465744 May 16 04:29:41 PM PDT 24 May 16 04:42:58 PM PDT 24 8090405003 ps
T700 /workspace/coverage/default/25.chip_sw_all_escalation_resets.3215684324 May 16 04:30:55 PM PDT 24 May 16 04:40:51 PM PDT 24 4809199152 ps
T120 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.4097650507 May 16 04:08:50 PM PDT 24 May 16 04:12:44 PM PDT 24 2582539608 ps
T933 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2175383005 May 16 04:23:22 PM PDT 24 May 16 04:29:58 PM PDT 24 3991687714 ps
T235 /workspace/coverage/default/27.chip_sw_all_escalation_resets.2785096727 May 16 04:27:14 PM PDT 24 May 16 04:35:09 PM PDT 24 4876000260 ps
T934 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1380619488 May 16 04:11:43 PM PDT 24 May 16 04:16:09 PM PDT 24 3309679203 ps
T56 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1870692269 May 16 04:09:30 PM PDT 24 May 16 04:16:19 PM PDT 24 4978239700 ps
T935 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3616768994 May 16 04:27:26 PM PDT 24 May 16 05:05:40 PM PDT 24 13085348284 ps
T611 /workspace/coverage/default/8.chip_sw_all_escalation_resets.567350726 May 16 04:26:29 PM PDT 24 May 16 04:36:13 PM PDT 24 5021781528 ps
T936 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1541230961 May 16 04:13:05 PM PDT 24 May 16 04:19:12 PM PDT 24 4327101256 ps
T937 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.19065497 May 16 04:30:46 PM PDT 24 May 16 04:37:19 PM PDT 24 4599251786 ps
T938 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2705592378 May 16 04:11:15 PM PDT 24 May 16 04:38:12 PM PDT 24 8962155786 ps
T939 /workspace/coverage/default/2.chip_sw_example_manufacturer.1965704448 May 16 04:23:24 PM PDT 24 May 16 04:26:44 PM PDT 24 2472003656 ps
T638 /workspace/coverage/default/67.chip_sw_all_escalation_resets.2028305599 May 16 04:37:47 PM PDT 24 May 16 04:48:05 PM PDT 24 6502078964 ps
T633 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3799609763 May 16 04:25:45 PM PDT 24 May 16 04:31:57 PM PDT 24 3481432472 ps
T940 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2126406719 May 16 04:26:10 PM PDT 24 May 16 04:30:11 PM PDT 24 2745016686 ps
T941 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2730882774 May 16 04:05:06 PM PDT 24 May 16 04:15:02 PM PDT 24 3788227576 ps
T284 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3058137563 May 16 04:24:22 PM PDT 24 May 16 04:28:02 PM PDT 24 2543464456 ps
T942 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1807788849 May 16 04:09:38 PM PDT 24 May 16 04:28:27 PM PDT 24 5827603944 ps
T696 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2803459818 May 16 04:31:41 PM PDT 24 May 16 04:40:37 PM PDT 24 5189262352 ps
T943 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.604441752 May 16 04:11:42 PM PDT 24 May 16 04:15:33 PM PDT 24 2863902615 ps
T944 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2632456849 May 16 04:07:37 PM PDT 24 May 16 04:13:15 PM PDT 24 2687159288 ps
T246 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3590242535 May 16 04:06:27 PM PDT 24 May 16 04:14:44 PM PDT 24 5402345000 ps
T945 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3224365998 May 16 04:11:17 PM PDT 24 May 16 04:14:34 PM PDT 24 2723951888 ps
T946 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.912126565 May 16 04:31:34 PM PDT 24 May 16 04:38:29 PM PDT 24 4460897136 ps
T28 /workspace/coverage/default/0.chip_sw_gpio.4143588322 May 16 04:02:51 PM PDT 24 May 16 04:09:41 PM PDT 24 4031382121 ps
T710 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2021317696 May 16 04:26:55 PM PDT 24 May 16 04:33:12 PM PDT 24 3934620860 ps
T247 /workspace/coverage/default/30.chip_sw_all_escalation_resets.144038780 May 16 04:27:56 PM PDT 24 May 16 04:39:31 PM PDT 24 5777482350 ps
T158 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2439446445 May 16 04:26:35 PM PDT 24 May 16 04:33:14 PM PDT 24 4743650250 ps
T947 /workspace/coverage/default/4.chip_tap_straps_prod.4285292544 May 16 04:31:55 PM PDT 24 May 16 04:40:40 PM PDT 24 5807257530 ps
T948 /workspace/coverage/default/0.chip_sw_kmac_entropy.1491159925 May 16 04:03:57 PM PDT 24 May 16 04:08:24 PM PDT 24 2864743760 ps
T949 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.137482133 May 16 04:08:50 PM PDT 24 May 16 07:13:05 PM PDT 24 255315435872 ps
T289 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1556170558 May 16 04:02:47 PM PDT 24 May 16 04:32:52 PM PDT 24 14485996610 ps
T375 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2096616616 May 16 04:23:45 PM PDT 24 May 16 04:32:40 PM PDT 24 4449527078 ps
T950 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2782492422 May 16 04:23:25 PM PDT 24 May 16 05:15:45 PM PDT 24 31924395000 ps
T951 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3649379263 May 16 04:29:29 PM PDT 24 May 16 04:51:43 PM PDT 24 8478327816 ps
T673 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3723510164 May 16 04:30:32 PM PDT 24 May 16 04:37:21 PM PDT 24 3970392920 ps
T171 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.837496916 May 16 04:24:06 PM PDT 24 May 16 04:31:10 PM PDT 24 4225494792 ps
T952 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.150296647 May 16 04:26:15 PM PDT 24 May 16 04:29:39 PM PDT 24 2460335352 ps
T12 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2680836227 May 16 04:03:18 PM PDT 24 May 16 04:08:53 PM PDT 24 2686217648 ps
T227 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2437167894 May 16 04:25:04 PM PDT 24 May 16 05:22:44 PM PDT 24 16876077956 ps
T248 /workspace/coverage/default/0.chip_sw_all_escalation_resets.1627023504 May 16 04:02:19 PM PDT 24 May 16 04:10:34 PM PDT 24 5226704488 ps
T476 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.4141119100 May 16 04:13:09 PM PDT 24 May 16 04:28:42 PM PDT 24 4670352718 ps
T652 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2899690111 May 16 04:30:12 PM PDT 24 May 16 04:36:58 PM PDT 24 3897832624 ps
T953 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.4075820684 May 16 04:26:39 PM PDT 24 May 16 04:33:27 PM PDT 24 5073181630 ps
T954 /workspace/coverage/default/15.chip_sw_all_escalation_resets.488697382 May 16 04:29:14 PM PDT 24 May 16 04:38:30 PM PDT 24 5928221106 ps
T674 /workspace/coverage/default/87.chip_sw_all_escalation_resets.2122176315 May 16 04:30:35 PM PDT 24 May 16 04:39:20 PM PDT 24 4968979048 ps
T955 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2194236336 May 16 04:24:44 PM PDT 24 May 16 05:15:49 PM PDT 24 19184553964 ps
T956 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.235542372 May 16 04:06:59 PM PDT 24 May 16 04:25:19 PM PDT 24 5398364267 ps
T23 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.4007584221 May 16 04:26:06 PM PDT 24 May 16 05:07:20 PM PDT 24 20574798191 ps
T957 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2292783492 May 16 04:22:11 PM PDT 24 May 16 04:43:15 PM PDT 24 8631012074 ps
T958 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3516822952 May 16 04:28:36 PM PDT 24 May 16 04:32:18 PM PDT 24 2560460120 ps
T959 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1036100838 May 16 04:04:13 PM PDT 24 May 16 04:29:14 PM PDT 24 13526890696 ps
T960 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.704420731 May 16 04:04:29 PM PDT 24 May 16 04:23:24 PM PDT 24 7954079823 ps
T961 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2991548901 May 16 04:13:06 PM PDT 24 May 16 04:50:51 PM PDT 24 22482451780 ps
T962 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3220672568 May 16 04:09:08 PM PDT 24 May 16 04:18:51 PM PDT 24 6043364358 ps
T963 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1498603451 May 16 04:10:26 PM PDT 24 May 16 04:14:45 PM PDT 24 3497630360 ps
T718 /workspace/coverage/default/32.chip_sw_all_escalation_resets.2869132345 May 16 04:28:15 PM PDT 24 May 16 04:35:35 PM PDT 24 4722694160 ps
T43 /workspace/coverage/default/2.rom_e2e_smoke.310483416 May 16 04:35:34 PM PDT 24 May 16 05:35:14 PM PDT 24 18112954110 ps
T659 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1818605762 May 16 04:28:44 PM PDT 24 May 16 04:35:09 PM PDT 24 4267908758 ps
T964 /workspace/coverage/default/21.chip_sw_all_escalation_resets.1687942600 May 16 04:29:30 PM PDT 24 May 16 04:39:14 PM PDT 24 5622784072 ps
T965 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1682579304 May 16 04:29:17 PM PDT 24 May 16 04:40:29 PM PDT 24 4460692184 ps
T966 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2736714137 May 16 04:33:04 PM PDT 24 May 16 04:37:52 PM PDT 24 3365737474 ps
T302 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1749138326 May 16 04:23:10 PM PDT 24 May 16 04:42:47 PM PDT 24 5798233252 ps
T244 /workspace/coverage/default/2.chip_sw_rv_timer_irq.103584783 May 16 04:23:14 PM PDT 24 May 16 04:27:10 PM PDT 24 2886868364 ps
T967 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1165533809 May 16 04:04:50 PM PDT 24 May 16 04:14:03 PM PDT 24 4342297952 ps
T968 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1399868905 May 16 04:11:54 PM PDT 24 May 16 04:21:32 PM PDT 24 4472563336 ps
T969 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2793063785 May 16 04:26:37 PM PDT 24 May 16 04:46:40 PM PDT 24 7537978740 ps
T970 /workspace/coverage/default/0.chip_sw_aes_smoketest.15688622 May 16 04:06:55 PM PDT 24 May 16 04:12:06 PM PDT 24 2922637152 ps
T294 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1228410898 May 16 04:02:59 PM PDT 24 May 16 04:11:40 PM PDT 24 4195135165 ps
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