Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.67 95.60 94.48 91.84 95.40 97.20 99.53


Total test records in report: 2735
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html
T121 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3690982527 May 16 04:04:25 PM PDT 24 May 16 04:14:12 PM PDT 24 4677009480 ps
T971 /workspace/coverage/default/2.chip_sw_aes_idle.3506272762 May 16 04:29:10 PM PDT 24 May 16 04:34:16 PM PDT 24 3377132960 ps
T692 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3870719402 May 16 04:28:13 PM PDT 24 May 16 04:33:35 PM PDT 24 3598137112 ps
T972 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1073089518 May 16 04:09:35 PM PDT 24 May 16 04:24:38 PM PDT 24 5507269576 ps
T645 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.4155007349 May 16 04:26:18 PM PDT 24 May 16 04:41:39 PM PDT 24 7280982472 ps
T144 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3661764114 May 16 04:06:30 PM PDT 24 May 16 04:32:26 PM PDT 24 22104605488 ps
T973 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1969410705 May 16 04:10:49 PM PDT 24 May 16 04:57:43 PM PDT 24 12256739632 ps
T665 /workspace/coverage/default/94.chip_sw_all_escalation_resets.2313528756 May 16 04:33:22 PM PDT 24 May 16 04:42:59 PM PDT 24 5939501720 ps
T623 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.985329829 May 16 04:03:22 PM PDT 24 May 16 04:33:37 PM PDT 24 22999265800 ps
T75 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3459973910 May 16 04:25:02 PM PDT 24 May 16 04:35:39 PM PDT 24 4277232008 ps
T974 /workspace/coverage/default/0.chip_tap_straps_prod.3667407147 May 16 04:07:11 PM PDT 24 May 16 04:20:39 PM PDT 24 8286667695 ps
T711 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3390210606 May 16 04:33:30 PM PDT 24 May 16 04:41:10 PM PDT 24 3879142458 ps
T975 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3527060069 May 16 04:03:46 PM PDT 24 May 16 04:56:47 PM PDT 24 35418646012 ps
T976 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1584985314 May 16 04:06:31 PM PDT 24 May 16 04:33:59 PM PDT 24 7370347316 ps
T52 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.4102931027 May 16 04:02:23 PM PDT 24 May 16 04:07:25 PM PDT 24 3213762352 ps
T295 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.4153123497 May 16 04:04:00 PM PDT 24 May 16 04:14:51 PM PDT 24 4203189656 ps
T977 /workspace/coverage/default/34.chip_sw_all_escalation_resets.3958226169 May 16 04:35:01 PM PDT 24 May 16 04:45:23 PM PDT 24 6245508530 ps
T978 /workspace/coverage/default/0.rom_keymgr_functest.619705941 May 16 04:07:21 PM PDT 24 May 16 04:18:13 PM PDT 24 4711546470 ps
T662 /workspace/coverage/default/52.chip_sw_all_escalation_resets.4237521911 May 16 04:28:30 PM PDT 24 May 16 04:37:56 PM PDT 24 5051264776 ps
T979 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2654584857 May 16 04:23:16 PM PDT 24 May 16 04:28:28 PM PDT 24 2232153620 ps
T663 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1266995722 May 16 04:29:42 PM PDT 24 May 16 04:35:34 PM PDT 24 3864198580 ps
T980 /workspace/coverage/default/1.chip_sw_hmac_smoketest.1716547309 May 16 04:22:45 PM PDT 24 May 16 04:30:07 PM PDT 24 3384805060 ps
T649 /workspace/coverage/default/57.chip_sw_all_escalation_resets.3613342823 May 16 04:29:11 PM PDT 24 May 16 04:38:27 PM PDT 24 4623154750 ps
T274 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.321678351 May 16 04:24:53 PM PDT 24 May 16 04:34:18 PM PDT 24 5051950350 ps
T981 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.564032896 May 16 04:10:19 PM PDT 24 May 16 04:35:45 PM PDT 24 6388258136 ps
T982 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3666310954 May 16 04:30:13 PM PDT 24 May 16 04:34:10 PM PDT 24 3043507844 ps
T983 /workspace/coverage/default/1.chip_sw_csrng_kat_test.4123823707 May 16 04:09:51 PM PDT 24 May 16 04:12:51 PM PDT 24 2711150870 ps
T666 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771337593 May 16 04:27:35 PM PDT 24 May 16 04:32:55 PM PDT 24 3244043156 ps
T984 /workspace/coverage/default/0.chip_sw_otbn_randomness.106774243 May 16 04:04:45 PM PDT 24 May 16 04:21:15 PM PDT 24 5617013096 ps
T709 /workspace/coverage/default/46.chip_sw_all_escalation_resets.1859237038 May 16 04:29:54 PM PDT 24 May 16 04:38:18 PM PDT 24 4198830152 ps
T275 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1086681240 May 16 04:03:46 PM PDT 24 May 16 04:11:12 PM PDT 24 3972355770 ps
T985 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1891540902 May 16 04:25:17 PM PDT 24 May 16 04:36:12 PM PDT 24 4556950832 ps
T164 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2080608903 May 16 04:12:12 PM PDT 24 May 16 04:17:22 PM PDT 24 4856214328 ps
T986 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1576465489 May 16 04:06:06 PM PDT 24 May 16 04:10:50 PM PDT 24 3417929996 ps
T667 /workspace/coverage/default/22.chip_sw_all_escalation_resets.4210156404 May 16 04:27:14 PM PDT 24 May 16 04:36:03 PM PDT 24 5544248056 ps
T987 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.102890482 May 16 04:24:00 PM PDT 24 May 16 04:44:15 PM PDT 24 11241712356 ps
T988 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.4137510516 May 16 04:26:45 PM PDT 24 May 16 04:48:35 PM PDT 24 8511589720 ps
T989 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1796586877 May 16 04:05:42 PM PDT 24 May 16 04:11:26 PM PDT 24 4956271100 ps
T990 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1412782585 May 16 04:25:45 PM PDT 24 May 16 04:46:44 PM PDT 24 5907890856 ps
T174 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1330294092 May 16 04:08:32 PM PDT 24 May 16 04:16:18 PM PDT 24 9336599744 ps
T991 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2942746720 May 16 04:10:39 PM PDT 24 May 16 04:19:06 PM PDT 24 3600561746 ps
T300 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3471983990 May 16 04:09:54 PM PDT 24 May 16 04:19:50 PM PDT 24 3887838984 ps
T631 /workspace/coverage/default/62.chip_sw_all_escalation_resets.2965001542 May 16 04:37:30 PM PDT 24 May 16 04:48:59 PM PDT 24 5793617528 ps
T653 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3616670730 May 16 04:27:10 PM PDT 24 May 16 04:32:19 PM PDT 24 3152310420 ps
T992 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3568391744 May 16 04:24:02 PM PDT 24 May 16 04:37:32 PM PDT 24 4386545300 ps
T993 /workspace/coverage/default/0.chip_sw_uart_smoketest.1514520879 May 16 04:09:30 PM PDT 24 May 16 04:14:11 PM PDT 24 3026184200 ps
T162 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3061464799 May 16 04:26:39 PM PDT 24 May 16 04:40:03 PM PDT 24 7999960342 ps
T994 /workspace/coverage/default/0.chip_sw_example_manufacturer.2385758329 May 16 04:03:06 PM PDT 24 May 16 04:07:36 PM PDT 24 3053882288 ps
T995 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1987633095 May 16 04:30:21 PM PDT 24 May 16 04:33:39 PM PDT 24 2690849014 ps
T996 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2745196574 May 16 04:09:22 PM PDT 24 May 16 04:15:49 PM PDT 24 7005873600 ps
T39 /workspace/coverage/default/2.chip_sw_spi_device_tpm.583775721 May 16 04:25:52 PM PDT 24 May 16 04:31:19 PM PDT 24 3854173848 ps
T377 /workspace/coverage/default/0.chip_sw_usbdev_stream.3928329610 May 16 04:02:30 PM PDT 24 May 16 05:13:15 PM PDT 24 19321389060 ps
T997 /workspace/coverage/default/0.chip_sw_power_idle_load.1461455447 May 16 04:05:07 PM PDT 24 May 16 04:14:24 PM PDT 24 4224544230 ps
T57 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3802153606 May 16 04:03:49 PM PDT 24 May 16 04:35:43 PM PDT 24 20656171570 ps
T684 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.801964061 May 16 04:29:44 PM PDT 24 May 16 04:35:16 PM PDT 24 3627902720 ps
T690 /workspace/coverage/default/58.chip_sw_all_escalation_resets.1893479361 May 16 04:29:23 PM PDT 24 May 16 04:37:19 PM PDT 24 4519797832 ps
T998 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2611363722 May 16 04:15:23 PM PDT 24 May 16 04:38:25 PM PDT 24 8938052269 ps
T999 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1827004845 May 16 04:21:40 PM PDT 24 May 16 04:41:21 PM PDT 24 5530027632 ps
T301 /workspace/coverage/default/2.chip_plic_all_irqs_20.1522066977 May 16 04:26:28 PM PDT 24 May 16 04:41:23 PM PDT 24 4743031784 ps
T1000 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2028768 May 16 04:04:55 PM PDT 24 May 16 04:14:09 PM PDT 24 4233752646 ps
T1001 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3964053951 May 16 04:03:30 PM PDT 24 May 16 04:13:47 PM PDT 24 3735882320 ps
T1002 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3830168373 May 16 04:05:20 PM PDT 24 May 16 04:24:38 PM PDT 24 6624808474 ps
T1003 /workspace/coverage/default/2.chip_sw_hmac_smoketest.75162583 May 16 04:28:17 PM PDT 24 May 16 04:34:12 PM PDT 24 2814488148 ps
T1004 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.589161599 May 16 04:06:32 PM PDT 24 May 16 05:03:03 PM PDT 24 24317830708 ps
T124 /workspace/coverage/default/1.chip_sw_alert_test.4283305698 May 16 04:11:52 PM PDT 24 May 16 04:16:29 PM PDT 24 3164695600 ps
T720 /workspace/coverage/default/66.chip_sw_all_escalation_resets.76917177 May 16 04:29:42 PM PDT 24 May 16 04:38:44 PM PDT 24 4852741018 ps
T1005 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1033122050 May 16 04:23:25 PM PDT 24 May 16 04:27:58 PM PDT 24 3169988480 ps
T238 /workspace/coverage/default/4.chip_sw_all_escalation_resets.1861322326 May 16 04:24:59 PM PDT 24 May 16 04:35:42 PM PDT 24 6257224816 ps
T1006 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2929283059 May 16 04:12:48 PM PDT 24 May 16 04:24:17 PM PDT 24 4070811178 ps
T697 /workspace/coverage/default/72.chip_sw_all_escalation_resets.4144800994 May 16 04:29:41 PM PDT 24 May 16 04:39:30 PM PDT 24 5215352400 ps
T1007 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3928080931 May 16 04:03:09 PM PDT 24 May 16 04:28:07 PM PDT 24 7867392564 ps
T134 /workspace/coverage/default/61.chip_sw_all_escalation_resets.3725766720 May 16 04:29:25 PM PDT 24 May 16 04:39:24 PM PDT 24 4326697972 ps
T602 /workspace/coverage/default/4.chip_tap_straps_dev.1334236616 May 16 04:26:57 PM PDT 24 May 16 04:40:27 PM PDT 24 9311265304 ps
T1008 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3186332210 May 16 04:30:34 PM PDT 24 May 16 04:38:13 PM PDT 24 3030416072 ps
T53 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1178744225 May 16 04:22:22 PM PDT 24 May 16 04:27:37 PM PDT 24 3042954790 ps
T1009 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2598104830 May 16 04:26:17 PM PDT 24 May 16 04:35:21 PM PDT 24 8039334168 ps
T1010 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3901534353 May 16 04:09:11 PM PDT 24 May 16 07:06:10 PM PDT 24 254178087944 ps
T1011 /workspace/coverage/default/1.chip_sw_power_sleep_load.546620465 May 16 04:17:30 PM PDT 24 May 16 04:29:55 PM PDT 24 10821362190 ps
T1012 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.349997941 May 16 04:24:03 PM PDT 24 May 16 04:45:19 PM PDT 24 7507559344 ps
T1013 /workspace/coverage/default/1.chip_sw_otbn_smoketest.3963494495 May 16 04:23:50 PM PDT 24 May 16 04:49:19 PM PDT 24 8441048740 ps
T1014 /workspace/coverage/default/0.chip_sw_hmac_enc.3218971131 May 16 04:05:05 PM PDT 24 May 16 04:10:51 PM PDT 24 2761134870 ps
T1015 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1099114833 May 16 04:04:13 PM PDT 24 May 16 04:11:18 PM PDT 24 3313546568 ps
T1016 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3000484184 May 16 04:27:09 PM PDT 24 May 16 04:31:23 PM PDT 24 2486203980 ps
T671 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.4184302636 May 16 04:29:50 PM PDT 24 May 16 04:36:21 PM PDT 24 3327689660 ps
T1017 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3104009261 May 16 04:24:21 PM PDT 24 May 16 04:34:54 PM PDT 24 3891275340 ps
T654 /workspace/coverage/default/60.chip_sw_all_escalation_resets.3926714633 May 16 04:29:26 PM PDT 24 May 16 04:40:51 PM PDT 24 5086890840 ps
T351 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.264637016 May 16 04:24:04 PM PDT 24 May 16 04:27:53 PM PDT 24 2528090840 ps
T702 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3070229046 May 16 04:30:22 PM PDT 24 May 16 04:37:28 PM PDT 24 3511326804 ps
T675 /workspace/coverage/default/96.chip_sw_all_escalation_resets.800430421 May 16 04:31:33 PM PDT 24 May 16 04:40:01 PM PDT 24 6257581680 ps
T1018 /workspace/coverage/default/1.chip_sw_example_flash.925299574 May 16 04:07:31 PM PDT 24 May 16 04:11:54 PM PDT 24 2464990456 ps
T1019 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1192916998 May 16 04:08:27 PM PDT 24 May 16 04:17:31 PM PDT 24 4572106944 ps
T1020 /workspace/coverage/default/1.chip_sw_example_manufacturer.951427094 May 16 04:10:02 PM PDT 24 May 16 04:15:07 PM PDT 24 2709785120 ps
T29 /workspace/coverage/default/2.chip_sw_gpio.3934550010 May 16 04:23:28 PM PDT 24 May 16 04:32:19 PM PDT 24 3884409492 ps
T1021 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1349452794 May 16 04:03:50 PM PDT 24 May 16 04:22:56 PM PDT 24 7761592536 ps
T1022 /workspace/coverage/default/2.chip_sw_kmac_smoketest.122920194 May 16 04:24:07 PM PDT 24 May 16 04:29:43 PM PDT 24 3136860202 ps
T634 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3312605706 May 16 04:31:56 PM PDT 24 May 16 04:41:50 PM PDT 24 5737796120 ps
T1023 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3003022397 May 16 04:08:08 PM PDT 24 May 16 04:11:29 PM PDT 24 2339511540 ps
T1024 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.600713318 May 16 04:25:08 PM PDT 24 May 16 04:35:36 PM PDT 24 5714046426 ps
T712 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1282773684 May 16 04:27:43 PM PDT 24 May 16 04:33:41 PM PDT 24 3550960416 ps
T40 /workspace/coverage/default/0.chip_sw_spi_device_tpm.2950175193 May 16 04:02:16 PM PDT 24 May 16 04:06:58 PM PDT 24 3174514311 ps
T1025 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2363838683 May 16 04:08:40 PM PDT 24 May 16 05:09:14 PM PDT 24 19233328956 ps
T686 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3368407655 May 16 04:33:27 PM PDT 24 May 16 04:42:21 PM PDT 24 5242505684 ps
T1026 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.961475894 May 16 04:25:25 PM PDT 24 May 16 04:31:00 PM PDT 24 3429210814 ps
T1027 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1087484192 May 16 04:24:35 PM PDT 24 May 16 04:58:31 PM PDT 24 10814908292 ps
T1028 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1367563368 May 16 04:11:32 PM PDT 24 May 16 04:18:15 PM PDT 24 4839277388 ps
T648 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3394858360 May 16 04:28:47 PM PDT 24 May 16 04:39:27 PM PDT 24 5250552960 ps
T1029 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1100232549 May 16 04:23:24 PM PDT 24 May 16 04:30:17 PM PDT 24 3048190898 ps
T658 /workspace/coverage/default/97.chip_sw_all_escalation_resets.3019532635 May 16 04:31:49 PM PDT 24 May 16 04:39:39 PM PDT 24 5666013568 ps
T324 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1179651849 May 16 04:26:41 PM PDT 24 May 16 04:31:43 PM PDT 24 3284402750 ps
T1030 /workspace/coverage/default/1.chip_sw_example_concurrency.194337268 May 16 04:07:23 PM PDT 24 May 16 04:12:15 PM PDT 24 3422664556 ps
T197 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3093662503 May 16 04:24:10 PM PDT 24 May 16 04:35:39 PM PDT 24 7725462272 ps
T1031 /workspace/coverage/default/0.chip_sw_aes_entropy.1904690874 May 16 04:04:28 PM PDT 24 May 16 04:08:55 PM PDT 24 2767321208 ps
T198 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2904377680 May 16 04:03:07 PM PDT 24 May 16 04:12:35 PM PDT 24 5034584043 ps
T35 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3994788153 May 16 04:22:31 PM PDT 24 May 16 04:27:01 PM PDT 24 3190797760 ps
T698 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1241815677 May 16 04:31:15 PM PDT 24 May 16 04:38:44 PM PDT 24 3753718488 ps
T1032 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3003731469 May 16 04:24:31 PM PDT 24 May 16 04:32:59 PM PDT 24 4616216822 ps
T1033 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4096167760 May 16 04:15:26 PM PDT 24 May 16 04:35:06 PM PDT 24 7597068835 ps
T287 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2858263705 May 16 04:10:24 PM PDT 24 May 16 04:22:55 PM PDT 24 8180875781 ps
T285 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1747944823 May 16 04:05:48 PM PDT 24 May 16 04:10:00 PM PDT 24 3048788629 ps
T1034 /workspace/coverage/default/2.chip_sw_aes_smoketest.401139567 May 16 04:25:38 PM PDT 24 May 16 04:30:31 PM PDT 24 2521288808 ps
T1035 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.226162383 May 16 04:28:57 PM PDT 24 May 16 04:32:58 PM PDT 24 3368868070 ps
T1036 /workspace/coverage/default/79.chip_sw_all_escalation_resets.476326634 May 16 04:33:30 PM PDT 24 May 16 04:41:37 PM PDT 24 5135226208 ps
T1037 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.482298830 May 16 04:06:22 PM PDT 24 May 16 04:16:40 PM PDT 24 4088549130 ps
T715 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1117016929 May 16 04:28:03 PM PDT 24 May 16 04:33:59 PM PDT 24 3263809320 ps
T1038 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2692641638 May 16 04:06:31 PM PDT 24 May 16 04:14:08 PM PDT 24 6363014700 ps
T1039 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1007690042 May 16 04:25:28 PM PDT 24 May 16 04:48:34 PM PDT 24 8472857792 ps
T1040 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.296802593 May 16 04:08:49 PM PDT 24 May 16 07:56:51 PM PDT 24 76607141670 ps
T76 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2324105719 May 16 04:04:00 PM PDT 24 May 16 04:15:30 PM PDT 24 5141823704 ps
T58 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.671494889 May 16 04:13:14 PM PDT 24 May 16 04:35:30 PM PDT 24 17894491926 ps
T168 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1037633382 May 16 04:16:46 PM PDT 24 May 16 04:55:33 PM PDT 24 18650491206 ps
T1041 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1446871295 May 16 04:23:51 PM PDT 24 May 16 04:27:45 PM PDT 24 3303335006 ps
T716 /workspace/coverage/default/35.chip_sw_all_escalation_resets.3360814698 May 16 04:30:56 PM PDT 24 May 16 04:37:33 PM PDT 24 5535411944 ps
T166 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2600194819 May 16 04:06:16 PM PDT 24 May 16 04:14:52 PM PDT 24 5300858822 ps
T1042 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.4181911069 May 16 04:22:45 PM PDT 24 May 16 04:30:03 PM PDT 24 5777480666 ps
T1043 /workspace/coverage/default/1.chip_sw_aes_masking_off.530528425 May 16 04:09:21 PM PDT 24 May 16 04:14:07 PM PDT 24 2454075473 ps
T122 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.4219646220 May 16 04:10:40 PM PDT 24 May 16 04:16:27 PM PDT 24 3691564136 ps
T276 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1156584164 May 16 04:23:53 PM PDT 24 May 16 04:31:14 PM PDT 24 3808666536 ps
T1044 /workspace/coverage/default/0.chip_sw_gpio_smoketest.3596083830 May 16 04:07:08 PM PDT 24 May 16 04:11:36 PM PDT 24 3593070540 ps
T305 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.273841443 May 16 04:26:16 PM PDT 24 May 16 04:39:31 PM PDT 24 5266321684 ps
T1045 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.603410897 May 16 04:26:03 PM PDT 24 May 16 04:30:24 PM PDT 24 2588310970 ps
T292 /workspace/coverage/default/2.chip_plic_all_irqs_0.1941660203 May 16 04:24:54 PM PDT 24 May 16 04:45:23 PM PDT 24 6491196240 ps
T1046 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3924007704 May 16 04:07:20 PM PDT 24 May 16 04:10:20 PM PDT 24 2402653538 ps
T1047 /workspace/coverage/default/1.chip_sw_rv_timer_irq.2370826697 May 16 04:12:31 PM PDT 24 May 16 04:16:15 PM PDT 24 2596918576 ps
T1048 /workspace/coverage/default/1.chip_tap_straps_prod.2223613457 May 16 04:14:55 PM PDT 24 May 16 04:24:58 PM PDT 24 6651613760 ps
T639 /workspace/coverage/default/90.chip_sw_all_escalation_resets.3933439501 May 16 04:32:21 PM PDT 24 May 16 04:40:48 PM PDT 24 5083977640 ps
T1049 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2043204481 May 16 04:08:53 PM PDT 24 May 16 04:13:00 PM PDT 24 3208405960 ps
T323 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2959503408 May 16 04:08:22 PM PDT 24 May 16 04:17:55 PM PDT 24 3926097972 ps
T330 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.275937239 May 16 04:23:52 PM PDT 24 May 16 04:31:38 PM PDT 24 3316728012 ps
T199 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1535527357 May 16 04:24:23 PM PDT 24 May 16 04:35:06 PM PDT 24 4783970065 ps
T318 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3541451030 May 16 04:10:03 PM PDT 24 May 16 04:24:21 PM PDT 24 5332974256 ps
T477 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4235980803 May 16 04:11:13 PM PDT 24 May 16 04:20:33 PM PDT 24 5370399436 ps
T687 /workspace/coverage/default/40.chip_sw_all_escalation_resets.1344283312 May 16 04:29:36 PM PDT 24 May 16 04:39:55 PM PDT 24 4872916340 ps
T107 /workspace/coverage/default/1.chip_plic_all_irqs_10.252316571 May 16 04:11:39 PM PDT 24 May 16 04:20:38 PM PDT 24 3724596450 ps
T353 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2266790142 May 16 04:07:18 PM PDT 24 May 16 04:18:04 PM PDT 24 5029401100 ps
T130 /workspace/coverage/default/0.chip_sw_usbdev_pullup.3601848417 May 16 04:04:49 PM PDT 24 May 16 04:08:37 PM PDT 24 3022641338 ps
T54 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.89004018 May 16 04:05:57 PM PDT 24 May 16 04:10:26 PM PDT 24 3186273416 ps
T676 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.619614071 May 16 04:29:39 PM PDT 24 May 16 04:35:54 PM PDT 24 3914557348 ps
T261 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.4086881052 May 16 04:26:07 PM PDT 24 May 16 04:34:47 PM PDT 24 9635493372 ps
T230 /workspace/coverage/default/2.chip_sw_flash_init.1205245931 May 16 04:24:59 PM PDT 24 May 16 05:00:33 PM PDT 24 20047354003 ps
T717 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3952569963 May 16 04:29:54 PM PDT 24 May 16 04:36:01 PM PDT 24 3904660936 ps
T239 /workspace/coverage/default/10.chip_sw_all_escalation_resets.102517046 May 16 04:25:35 PM PDT 24 May 16 04:33:27 PM PDT 24 5573857536 ps
T1050 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.632790084 May 16 04:04:14 PM PDT 24 May 16 04:10:32 PM PDT 24 3510715256 ps
T341 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2533224168 May 16 04:30:45 PM PDT 24 May 16 04:37:01 PM PDT 24 3176258804 ps
T1051 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.4138700854 May 16 04:28:09 PM PDT 24 May 16 04:35:01 PM PDT 24 3478142692 ps
T288 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3172841060 May 16 04:04:49 PM PDT 24 May 16 04:18:17 PM PDT 24 8201666596 ps
T306 /workspace/coverage/default/0.chip_plic_all_irqs_20.1094637404 May 16 04:08:20 PM PDT 24 May 16 04:23:06 PM PDT 24 3922971074 ps
T1052 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.4249885037 May 16 04:25:16 PM PDT 24 May 16 04:36:17 PM PDT 24 4540516679 ps
T1053 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.983557214 May 16 04:09:23 PM PDT 24 May 16 04:13:08 PM PDT 24 2690439804 ps
T703 /workspace/coverage/default/51.chip_sw_all_escalation_resets.21044631 May 16 04:31:51 PM PDT 24 May 16 04:39:55 PM PDT 24 5634091504 ps
T1054 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3530269356 May 16 04:22:25 PM PDT 24 May 16 04:25:52 PM PDT 24 3022979970 ps
T1055 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.958196607 May 16 04:09:05 PM PDT 24 May 16 04:45:52 PM PDT 24 18344191937 ps
T691 /workspace/coverage/default/80.chip_sw_all_escalation_resets.352314811 May 16 04:29:08 PM PDT 24 May 16 04:36:18 PM PDT 24 5051636472 ps
T1056 /workspace/coverage/default/0.chip_sw_example_flash.1269404961 May 16 04:02:24 PM PDT 24 May 16 04:06:18 PM PDT 24 2758500554 ps
T55 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.195966668 May 16 04:23:21 PM PDT 24 May 16 04:28:07 PM PDT 24 3055920140 ps
T249 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1362034055 May 16 04:23:00 PM PDT 24 May 16 04:34:50 PM PDT 24 5384472220 ps
T1057 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.7904946 May 16 04:11:55 PM PDT 24 May 16 04:21:29 PM PDT 24 4879316064 ps
T660 /workspace/coverage/default/29.chip_sw_all_escalation_resets.2671874686 May 16 04:33:39 PM PDT 24 May 16 04:43:40 PM PDT 24 4500279032 ps
T1058 /workspace/coverage/default/0.chip_sw_kmac_app_rom.1365338225 May 16 04:03:34 PM PDT 24 May 16 04:06:26 PM PDT 24 2373564234 ps
T1059 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3597263036 May 16 04:09:59 PM PDT 24 May 16 04:13:52 PM PDT 24 3014973293 ps
T1060 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.78099844 May 16 04:22:16 PM PDT 24 May 16 07:47:21 PM PDT 24 76883688010 ps
T672 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3907623953 May 16 04:31:51 PM PDT 24 May 16 04:39:32 PM PDT 24 5891447816 ps
T1061 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3727317757 May 16 04:26:13 PM PDT 24 May 16 04:47:26 PM PDT 24 8990695016 ps
T1062 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.141301789 May 16 04:05:38 PM PDT 24 May 16 04:17:50 PM PDT 24 8015449268 ps
T1063 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.862356282 May 16 04:08:46 PM PDT 24 May 16 04:12:10 PM PDT 24 3119677891 ps
T1064 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.762804041 May 16 04:24:49 PM PDT 24 May 16 04:33:10 PM PDT 24 3350100786 ps
T635 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.843752916 May 16 04:30:48 PM PDT 24 May 16 04:36:41 PM PDT 24 3833894520 ps
T1065 /workspace/coverage/default/1.chip_sw_gpio_smoketest.216452467 May 16 04:28:24 PM PDT 24 May 16 04:32:39 PM PDT 24 2683874842 ps
T325 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3236098000 May 16 04:06:56 PM PDT 24 May 16 04:11:23 PM PDT 24 2643015486 ps
T1066 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4243157505 May 16 04:22:52 PM PDT 24 May 16 04:50:11 PM PDT 24 11426691300 ps
T1067 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2050674585 May 16 04:06:03 PM PDT 24 May 16 04:09:16 PM PDT 24 3107943052 ps
T1068 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2727244195 May 16 04:08:18 PM PDT 24 May 16 04:12:16 PM PDT 24 2991555399 ps
T1069 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1016597040 May 16 04:15:37 PM PDT 24 May 16 04:22:42 PM PDT 24 3381460996 ps
T1070 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1380425430 May 16 04:12:22 PM PDT 24 May 16 04:25:58 PM PDT 24 6831002882 ps
T1071 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1980263672 May 16 04:24:16 PM PDT 24 May 16 04:37:11 PM PDT 24 4667276496 ps
T1072 /workspace/coverage/default/1.chip_sw_aes_enc.2304998171 May 16 04:11:49 PM PDT 24 May 16 04:16:16 PM PDT 24 2953318744 ps
T1073 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.763596064 May 16 04:02:12 PM PDT 24 May 16 04:11:11 PM PDT 24 4206970851 ps
T1074 /workspace/coverage/default/64.chip_sw_all_escalation_resets.3642651135 May 16 04:29:56 PM PDT 24 May 16 04:37:54 PM PDT 24 5811431976 ps
T629 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3606881830 May 16 04:33:39 PM PDT 24 May 16 04:40:22 PM PDT 24 4252575880 ps
T699 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.4028054996 May 16 04:27:15 PM PDT 24 May 16 04:32:29 PM PDT 24 3901053046 ps
T1075 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3609058691 May 16 04:27:42 PM PDT 24 May 16 04:39:29 PM PDT 24 4385219088 ps
T51 /workspace/coverage/default/0.chip_jtag_csr_rw.2772763535 May 16 03:56:14 PM PDT 24 May 16 04:33:42 PM PDT 24 20579070038 ps
T1076 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1621679271 May 16 04:03:40 PM PDT 24 May 16 04:10:10 PM PDT 24 4628266320 ps
T590 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1811704201 May 16 04:09:20 PM PDT 24 May 16 04:13:12 PM PDT 24 2893086952 ps
T656 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3938205002 May 16 04:31:32 PM PDT 24 May 16 04:37:31 PM PDT 24 3298939268 ps
T1077 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1673419389 May 16 04:23:59 PM PDT 24 May 16 04:51:17 PM PDT 24 18971879408 ps
T1078 /workspace/coverage/default/1.rom_keymgr_functest.1727459408 May 16 04:21:58 PM PDT 24 May 16 04:31:50 PM PDT 24 5814500508 ps
T1079 /workspace/coverage/default/0.chip_sw_rv_timer_irq.75169328 May 16 04:05:39 PM PDT 24 May 16 04:09:48 PM PDT 24 3176683912 ps
T38 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.68773559 May 16 04:08:54 PM PDT 24 May 16 04:17:01 PM PDT 24 5285876968 ps
T1080 /workspace/coverage/default/2.chip_sw_power_idle_load.12830668 May 16 04:25:14 PM PDT 24 May 16 04:37:20 PM PDT 24 3920890516 ps
T670 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4249624664 May 16 04:28:51 PM PDT 24 May 16 04:35:11 PM PDT 24 3740526024 ps
T1081 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2085365674 May 16 04:31:03 PM PDT 24 May 16 04:44:17 PM PDT 24 4991222668 ps
T1082 /workspace/coverage/default/0.chip_sw_hmac_smoketest.4259425152 May 16 04:08:11 PM PDT 24 May 16 04:13:59 PM PDT 24 2696686732 ps
T705 /workspace/coverage/default/48.chip_sw_all_escalation_resets.558638478 May 16 04:28:19 PM PDT 24 May 16 04:37:53 PM PDT 24 5032924990 ps
T108 /workspace/coverage/default/2.chip_plic_all_irqs_10.1995421460 May 16 04:27:14 PM PDT 24 May 16 04:35:48 PM PDT 24 3887946964 ps
T1083 /workspace/coverage/default/0.chip_sw_usbdev_dpi.1615818331 May 16 04:03:17 PM PDT 24 May 16 04:48:13 PM PDT 24 12159105540 ps
T1084 /workspace/coverage/default/50.chip_sw_all_escalation_resets.3599934111 May 16 04:30:37 PM PDT 24 May 16 04:41:04 PM PDT 24 4418179936 ps
T72 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.256893206 May 16 04:23:28 PM PDT 24 May 16 04:33:16 PM PDT 24 6177455040 ps
T1085 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1520321342 May 16 04:08:36 PM PDT 24 May 16 04:29:25 PM PDT 24 6265782600 ps
T1086 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3911202206 May 16 04:05:36 PM PDT 24 May 16 04:15:11 PM PDT 24 3356022386 ps
T1087 /workspace/coverage/default/70.chip_sw_all_escalation_resets.2392653019 May 16 04:32:35 PM PDT 24 May 16 04:42:22 PM PDT 24 5605857122 ps
T1088 /workspace/coverage/default/0.chip_sw_csrng_kat_test.3345227547 May 16 04:09:38 PM PDT 24 May 16 04:15:15 PM PDT 24 3102877560 ps
T1089 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2438668858 May 16 04:16:33 PM PDT 24 May 16 04:26:08 PM PDT 24 5298337262 ps
T1090 /workspace/coverage/default/1.chip_sw_csrng_smoketest.829361184 May 16 04:21:50 PM PDT 24 May 16 04:26:40 PM PDT 24 3297778568 ps
T1091 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2349587207 May 16 04:24:01 PM PDT 24 May 16 04:40:42 PM PDT 24 5984866768 ps
T1092 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.724756314 May 16 04:10:42 PM PDT 24 May 16 04:27:50 PM PDT 24 4952669000 ps
T693 /workspace/coverage/default/65.chip_sw_all_escalation_resets.957816402 May 16 04:33:16 PM PDT 24 May 16 04:43:10 PM PDT 24 5202019960 ps
T1093 /workspace/coverage/default/3.chip_sw_uart_tx_rx.2089107463 May 16 04:26:46 PM PDT 24 May 16 04:35:34 PM PDT 24 4105881352 ps
T1094 /workspace/coverage/default/2.chip_sw_power_sleep_load.2258895946 May 16 04:24:37 PM PDT 24 May 16 04:33:54 PM PDT 24 8945007092 ps
T1095 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.164270271 May 16 04:25:52 PM PDT 24 May 16 04:34:36 PM PDT 24 7911605080 ps
T214 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.569269312 May 16 04:04:46 PM PDT 24 May 16 04:55:40 PM PDT 24 20797365252 ps
T1096 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1880794470 May 16 04:14:42 PM PDT 24 May 16 04:25:52 PM PDT 24 4114324664 ps
T44 /workspace/coverage/default/0.rom_e2e_smoke.1286019326 May 16 04:10:34 PM PDT 24 May 16 05:16:57 PM PDT 24 17478240910 ps
T1097 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2097654480 May 16 04:33:29 PM PDT 24 May 16 04:39:14 PM PDT 24 3640650520 ps
T1098 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2117924963 May 16 04:13:10 PM PDT 24 May 16 04:27:28 PM PDT 24 5783522024 ps
T1099 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3086697603 May 16 04:08:11 PM PDT 24 May 16 04:12:27 PM PDT 24 2495072593 ps
T215 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3136834864 May 16 04:10:12 PM PDT 24 May 16 05:06:12 PM PDT 24 20799490431 ps
T1100 /workspace/coverage/default/36.chip_sw_all_escalation_resets.3315160424 May 16 04:28:14 PM PDT 24 May 16 04:38:37 PM PDT 24 6015254576 ps
T1101 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.4156929955 May 16 04:06:02 PM PDT 24 May 16 04:10:44 PM PDT 24 3428391570 ps
T622 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1111379880 May 16 04:05:23 PM PDT 24 May 16 04:18:19 PM PDT 24 4463367096 ps
T1102 /workspace/coverage/default/11.chip_sw_all_escalation_resets.2438557640 May 16 04:26:38 PM PDT 24 May 16 04:35:43 PM PDT 24 5610328370 ps
T1103 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.695305936 May 16 04:22:49 PM PDT 24 May 16 04:40:08 PM PDT 24 5620770646 ps
T1104 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3151026511 May 16 04:24:07 PM PDT 24 May 16 04:49:44 PM PDT 24 9280021676 ps
T123 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1036785462 May 16 04:26:55 PM PDT 24 May 16 04:37:07 PM PDT 24 4855230912 ps
T1105 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2913131961 May 16 04:03:44 PM PDT 24 May 16 04:07:44 PM PDT 24 3045688413 ps
T1106 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1317211610 May 16 04:13:54 PM PDT 24 May 16 04:16:56 PM PDT 24 2424311817 ps
T1107 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3669018179 May 16 04:09:09 PM PDT 24 May 16 04:16:19 PM PDT 24 19593536878 ps
T1108 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3668127710 May 16 04:04:32 PM PDT 24 May 16 04:35:56 PM PDT 24 12712902866 ps
T1109 /workspace/coverage/default/1.chip_tap_straps_rma.142852328 May 16 04:13:33 PM PDT 24 May 16 04:18:58 PM PDT 24 4076424886 ps
T706 /workspace/coverage/default/18.chip_sw_all_escalation_resets.1911762766 May 16 04:25:20 PM PDT 24 May 16 04:35:36 PM PDT 24 5975301420 ps
T1110 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2560069907 May 16 04:05:34 PM PDT 24 May 16 04:16:38 PM PDT 24 19941389968 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%