Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3756182	1			T62	1920		T63	86		T64	497
values[2]	741914	1			T62	548		T63	30		T64	1018
values[3]	103867	1			T62	19		T63	3		T64	543
values[4]	54716	1			T62	1		T64	243		T66	234
values[5]	38005	1			T64	181		T66	170		T234	113
values[6]	28458	1			T64	129		T66	107		T234	90
values[7]	23528	1			T64	109		T66	81		T234	109
values[8]	19912	1			T64	96		T66	58		T234	125
values[9]	17682	1			T64	107		T66	56		T234	127
values[10]	16112	1			T64	90		T66	25		T234	137
values[11]	14790	1			T64	58		T66	9		T234	103
values[12]	13740	1			T64	55		T66	10		T234	120
values[13]	13156	1			T64	42		T66	20		T234	126
values[14]	12382	1			T64	44		T66	15		T234	76
values[15]	12149	1			T64	59		T66	9		T234	83
values[16]	11565	1			T64	42		T66	10		T234	79
values[17]	11219	1			T64	69		T66	20		T234	75
values[18]	10935	1			T64	60		T66	14		T234	78
values[19]	10732	1			T64	69		T66	14		T234	98
values[20]	10284	1			T64	55		T66	16		T234	98
values[21]	10272	1			T64	52		T66	16		T234	86
values[22]	9854	1			T64	40		T66	15		T234	80
values[23]	9577	1			T64	37		T66	12		T234	72
values[24]	9124	1			T64	32		T66	15		T234	51
values[25]	8543	1			T64	17		T66	13		T234	47
values[26]	8283	1			T64	20		T66	15		T234	53
values[27]	7914	1			T64	25		T66	21		T234	49
values[28]	7491	1			T64	18		T66	14		T234	48
values[29]	7114	1			T64	34		T66	11		T234	63
values[30]	6712	1			T64	21		T66	23		T234	58
values[31]	6297	1			T64	24		T66	19		T234	47
values[32]	5694	1			T64	14		T66	18		T234	52
values[33]	5255	1			T64	28		T66	9		T234	44
values[34]	4926	1			T64	26		T66	11		T234	27
values[35]	4793	1			T64	40		T66	8		T234	24
values[36]	4496	1			T64	33		T66	10		T234	13
values[37]	4164	1			T64	24		T66	11		T234	30
values[38]	3843	1			T64	23		T66	8		T234	20
values[39]	3871	1			T64	33		T66	10		T234	8
values[40]	3695	1			T64	23		T66	14		T234	9
values[41]	3703	1			T64	21		T66	12		T234	7
values[42]	3534	1			T64	18		T66	18		T234	10
values[43]	3414	1			T64	19		T66	17		T234	7
values[44]	3386	1			T64	24		T66	30		T234	5
values[45]	3263	1			T64	28		T66	14		T234	11
values[46]	3237	1			T64	15		T66	13		T234	7
values[47]	3196	1			T64	14		T66	10		T234	7
values[48]	3080	1			T64	13		T66	14		T234	6
values[49]	3051	1			T64	13		T66	16		T234	5
values[50]	2984	1			T64	13		T66	7		T234	7
values[51]	2933	1			T64	10		T66	10		T234	6
values[52]	2883	1			T64	9		T66	10		T234	3
values[53]	2788	1			T64	14		T66	11		T234	5
values[54]	2678	1			T64	12		T66	13		T234	3
values[55]	2679	1			T64	16		T66	9		T234	6
values[56]	2719	1			T64	16		T66	16		T234	3
values[57]	2619	1			T64	12		T66	17		T234	6
values[58]	2511	1			T64	17		T66	13		T234	7
values[59]	2470	1			T64	7		T66	15		T234	6
values[60]	2495	1			T64	15		T66	8		T234	2
values[61]	2770	1			T64	24		T66	12		T234	2
values[62]	4533	1			T64	59		T66	27		T234	3
values[63]	16836	1			T64	234		T66	75		T234	9
values[64]	236151	1			T64	248		T66	213		T234	264

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4836031	1			T62	1973		T63	126		T64	3261
values[2]	789856	1			T62	430		T63	20		T64	758
values[3]	74120	1			T62	25		T63	4		T64	78
values[4]	13627	1			T62	1		T64	23		T66	11
values[5]	5608	1			T64	39		T66	1		T234	5
values[6]	3384	1			T64	24		T234	3		T395	44
values[7]	2525	1			T64	15		T234	2		T395	45
values[8]	2116	1			T64	22		T234	4		T395	27
values[9]	1800	1			T64	18		T234	4		T395	41
values[10]	1582	1			T64	23		T234	4		T395	27
values[11]	1439	1			T64	36		T234	3		T395	12
values[12]	1263	1			T64	34		T234	5		T395	20
values[13]	1241	1			T64	27		T234	4		T395	13
values[14]	1348	1			T64	21		T234	5		T395	11
values[15]	1280	1			T64	24		T234	3		T395	19
values[16]	1123	1			T64	19		T234	2		T395	16
values[17]	951	1			T64	16		T234	2		T395	12
values[18]	928	1			T64	14		T234	4		T395	29
values[19]	895	1			T64	19		T234	3		T395	22
values[20]	792	1			T64	23		T234	4		T395	21
values[21]	811	1			T64	15		T234	2		T395	23
values[22]	805	1			T64	15		T234	2		T395	25
values[23]	763	1			T64	21		T234	2		T395	25
values[24]	735	1			T64	10		T234	2		T395	9
values[25]	694	1			T64	12		T234	2		T395	1
values[26]	713	1			T64	9		T234	4		T395	2
values[27]	638	1			T64	5		T234	3		T395	2
values[28]	623	1			T64	1		T234	5		T395	2
values[29]	586	1			T64	1		T234	2		T395	1
values[30]	577	1			T64	1		T234	6		T395	1
values[31]	519	1			T64	1		T234	3		T395	2
values[32]	563	1			T64	4		T234	4		T395	2
values[33]	569	1			T64	3		T234	8		T395	1
values[34]	536	1			T64	4		T234	2		T395	2
values[35]	550	1			T64	4		T234	3		T395	3
values[36]	522	1			T64	3		T234	5		T395	1
values[37]	526	1			T64	1		T234	4		T395	1
values[38]	490	1			T64	1		T234	7		T395	5
values[39]	496	1			T64	7		T234	3		T395	1
values[40]	507	1			T64	7		T234	7		T395	2
values[41]	474	1			T64	2		T234	6		T395	1
values[42]	454	1			T64	9		T234	4		T395	2
values[43]	450	1			T64	7		T234	3		T395	1
values[44]	448	1			T64	4		T234	5		T395	1
values[45]	450	1			T64	2		T234	3		T395	1
values[46]	448	1			T234	6		T395	1		T412	2
values[47]	460	1			T234	2		T395	2		T412	2
values[48]	408	1			T234	5		T395	2		T412	2
values[49]	435	1			T234	4		T395	1		T412	2
values[50]	410	1			T234	5		T395	2		T412	2
values[51]	405	1			T234	6		T395	2		T412	2
values[52]	439	1			T234	3		T395	5		T412	2
values[53]	402	1			T234	3		T395	3		T412	2
values[54]	391	1			T234	3		T395	1		T412	2
values[55]	379	1			T234	5		T395	1		T412	2
values[56]	393	1			T234	2		T395	1		T412	2
values[57]	376	1			T234	7		T395	1		T412	2
values[58]	355	1			T234	5		T395	4		T412	2
values[59]	360	1			T234	4		T395	1		T412	2
values[60]	379	1			T234	2		T395	2		T412	2
values[61]	409	1			T234	6		T395	3		T412	2
values[62]	675	1			T234	2		T395	3		T412	2
values[63]	3145	1			T234	10		T395	40		T412	2
values[64]	28350	1			T234	239		T395	112		T412	363

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	626915	1			T62	20		T63	3		T64	19
values[2]	2694850	1			T62	898		T63	132		T64	354
values[3]	1114218	1			T62	1567		T63	52		T64	871
values[4]	141180	1			T62	31		T63	2		T64	432
values[5]	73555	1			T64	278		T105	7		T66	218
values[6]	48402	1			T64	181		T66	106		T234	159
values[7]	35574	1			T64	152		T66	59		T234	129
values[8]	28333	1			T64	105		T66	46		T234	131
values[9]	24084	1			T64	119		T66	40		T234	139
values[10]	21468	1			T64	89		T66	38		T234	91
values[11]	19405	1			T64	86		T66	18		T234	100
values[12]	17552	1			T64	72		T66	21		T234	94
values[13]	16672	1			T64	63		T66	12		T234	65
values[14]	16049	1			T64	76		T66	22		T234	80
values[15]	15041	1			T64	64		T66	14		T234	121
values[16]	14032	1			T64	41		T66	12		T234	98
values[17]	13214	1			T64	53		T66	13		T234	110
values[18]	12985	1			T64	63		T66	16		T234	79
values[19]	12335	1			T64	66		T66	25		T234	81
values[20]	11877	1			T64	46		T66	22		T234	61
values[21]	11415	1			T64	40		T66	17		T234	79
values[22]	10740	1			T64	39		T66	12		T234	67
values[23]	10401	1			T64	58		T66	13		T234	81
values[24]	9993	1			T64	59		T66	18		T234	70
values[25]	9595	1			T64	65		T66	18		T234	91
values[26]	9041	1			T64	63		T66	14		T234	69
values[27]	8617	1			T64	36		T66	9		T234	89
values[28]	8013	1			T64	27		T66	14		T234	102
values[29]	7622	1			T64	21		T66	11		T234	71
values[30]	7491	1			T64	24		T66	18		T234	102
values[31]	6786	1			T64	21		T66	29		T234	66
values[32]	6430	1			T64	28		T66	30		T234	44
values[33]	5911	1			T64	32		T66	19		T234	31
values[34]	5504	1			T64	23		T66	9		T234	38
values[35]	5014	1			T64	14		T66	12		T234	12
values[36]	4820	1			T64	6		T66	12		T234	25
values[37]	4583	1			T64	9		T66	9		T234	28
values[38]	4385	1			T64	13		T66	10		T234	21
values[39]	4158	1			T64	25		T66	13		T234	14
values[40]	4117	1			T64	14		T66	8		T234	7
values[41]	3897	1			T64	18		T66	10		T234	15
values[42]	3796	1			T64	12		T66	12		T234	14
values[43]	3675	1			T64	22		T66	11		T234	15
values[44]	3595	1			T64	17		T66	8		T234	11
values[45]	3620	1			T64	13		T66	13		T234	13
values[46]	3491	1			T64	12		T66	17		T234	10
values[47]	3524	1			T64	20		T66	32		T234	3
values[48]	3328	1			T64	19		T66	16		T234	5
values[49]	3279	1			T64	10		T66	21		T234	3
values[50]	3254	1			T64	13		T66	9		T234	7
values[51]	3265	1			T64	15		T66	9		T234	5
values[52]	3211	1			T64	16		T66	7		T234	5
values[53]	3215	1			T64	15		T66	7		T234	7
values[54]	3124	1			T64	13		T66	5		T234	2
values[55]	3106	1			T64	20		T66	6		T234	1
values[56]	2993	1			T64	22		T66	11		T234	3
values[57]	2998	1			T64	17		T66	8		T234	2
values[58]	2810	1			T64	9		T66	8		T234	1
values[59]	2805	1			T64	17		T66	10		T234	2
values[60]	2740	1			T64	9		T66	9		T234	3
values[61]	2931	1			T64	14		T66	15		T234	2
values[62]	4114	1			T64	25		T66	23		T234	1
values[63]	20500	1			T64	107		T66	70		T234	2
values[64]	223629	1			T64	239		T66	116		T234	142