Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1913224	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26107810

1

T1

8233

T2

14698

T3

6174

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19140414	1			T1	3921		T2	7946		T3	2704
values[0x0]	7497229	1			T1	4312		T2	6752		T3	3470
values[0x1]	1383391	1			T1	475		T2	911		T3	423

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	612997	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

27408037

1

T1

8708

T2

15609

T3

6597

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12936146	1			T1	4354		T2	7805		T3	3299
valid_sources[0x01]	12933785	1			T1	4354		T2	7804		T3	3298
valid_sources[0x02]	34018	1			T45	3		T51	1		T190	1
valid_sources[0x03]	35229	1			T45	1		T51	2		T65	1
valid_sources[0x04]	34468	1			T45	1		T179	94		T358	378
valid_sources[0x05]	34985	1			T190	2		T179	101		T358	331
valid_sources[0x06]	34375	1			T44	2		T45	1		T51	1
valid_sources[0x07]	34599	1			T44	3		T51	1		T190	2
valid_sources[0x08]	34844	1			T45	1		T179	166		T358	342
valid_sources[0x09]	33869	1			T54	1		T190	1		T65	3
valid_sources[0x0a]	34430	1			T54	1		T65	2		T179	75
valid_sources[0x0b]	34082	1			T44	3		T65	3		T179	89
valid_sources[0x0c]	34307	1			T44	1		T45	1		T51	1
valid_sources[0x0d]	34663	1			T44	1		T51	1		T190	2
valid_sources[0x0e]	34666	1			T65	1		T179	68		T358	313
valid_sources[0x0f]	33900	1			T45	1		T54	4		T65	4
valid_sources[0x10]	34754	1			T51	2		T65	1		T179	71
valid_sources[0x11]	35183	1			T44	2		T45	1		T51	2
valid_sources[0x12]	34617	1			T44	1		T179	77		T358	352
valid_sources[0x13]	33932	1			T44	1		T45	1		T190	1
valid_sources[0x14]	34713	1			T51	1		T190	1		T65	1
valid_sources[0x15]	34335	1			T179	64		T358	356		T182	89
valid_sources[0x16]	34214	1			T44	2		T190	3		T65	1
valid_sources[0x17]	34462	1			T51	3		T259	2		T190	1
valid_sources[0x18]	35552	1			T45	2		T65	459		T179	43
valid_sources[0x19]	34603	1			T44	1		T45	3		T51	1
valid_sources[0x1a]	34391	1			T44	2		T54	1		T65	2
valid_sources[0x1b]	34452	1			T44	1		T45	1		T51	2
valid_sources[0x1c]	35389	1			T51	1		T54	1		T179	160
valid_sources[0x1d]	35496	1			T44	1		T51	2		T259	5
valid_sources[0x1e]	35184	1			T45	1		T179	62		T358	369
valid_sources[0x1f]	38825	1			T51	1		T179	108		T358	377
valid_sources[0x20]	33879	1			T54	4		T65	1		T179	76

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18448033

1

T1

3921

T2

7946

T3

2704

values[0x0]

all_enables

biggest_size

7455061

1

T1

4312

T2

6752

T3

3470

values[0x1]

all_enables

biggest_size

204716

1

T44

21

T45

18

T51

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2897442	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

458666

1

T62

337

T63

25

T64

687

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1135464	1			T62	846		T63	43		T64	1698
values[0x0]	1082861	1			T62	780		T63	45		T64	1650
values[0x1]	1137783	1			T62	862		T63	31		T64	1653

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2243519	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1112589

1

T62

818

T63

44

T64

1618

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51198	1			T62	32		T63	2		T64	78
valid_sources[0x01]	51967	1			T62	38		T63	2		T64	102
valid_sources[0x02]	51868	1			T62	43		T63	2		T64	72
valid_sources[0x03]	53072	1			T62	38		T63	3		T64	74
valid_sources[0x04]	52307	1			T62	22		T63	1		T64	75
valid_sources[0x05]	51985	1			T62	29		T63	1		T64	78
valid_sources[0x06]	52650	1			T62	34		T63	4		T64	76
valid_sources[0x07]	52105	1			T62	66		T63	1		T64	86
valid_sources[0x08]	52694	1			T62	42		T64	70		T66	8
valid_sources[0x09]	51564	1			T62	51		T64	78		T66	7
valid_sources[0x0a]	53888	1			T62	45		T63	2		T64	88
valid_sources[0x0b]	51545	1			T62	28		T63	3		T64	75
valid_sources[0x0c]	52650	1			T62	52		T63	2		T64	86
valid_sources[0x0d]	52984	1			T62	24		T63	1		T64	76
valid_sources[0x0e]	52888	1			T62	50		T63	2		T64	65
valid_sources[0x0f]	52903	1			T62	51		T64	75		T397	4
valid_sources[0x10]	52274	1			T62	60		T64	76		T72	5
valid_sources[0x11]	51941	1			T62	44		T63	4		T64	81
valid_sources[0x12]	52369	1			T62	47		T63	2		T64	83
valid_sources[0x13]	52333	1			T62	51		T63	2		T64	85
valid_sources[0x14]	52695	1			T62	46		T63	2		T64	64
valid_sources[0x15]	52688	1			T62	43		T64	71		T72	2
valid_sources[0x16]	53010	1			T62	29		T63	1		T64	87
valid_sources[0x17]	52682	1			T62	34		T63	3		T64	73
valid_sources[0x18]	53491	1			T62	30		T63	3		T64	74
valid_sources[0x19]	52502	1			T62	41		T63	4		T64	81
valid_sources[0x1a]	52708	1			T62	42		T63	1		T64	71
valid_sources[0x1b]	52412	1			T62	29		T63	1		T64	66
valid_sources[0x1c]	52823	1			T62	43		T63	2		T64	68
valid_sources[0x1d]	52106	1			T62	36		T63	2		T64	80
valid_sources[0x1e]	52460	1			T62	52		T64	76		T72	4
valid_sources[0x1f]	53061	1			T62	35		T63	2		T64	68
valid_sources[0x20]	52259	1			T62	44		T63	3		T64	75

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47880

1

T62

36

T63

2

T64

80

values[0x0]

all_enables

biggest_size

362515

1

T62

255

T63

21

T64

539

values[0x1]

all_enables

biggest_size

48271

1

T62

46

T63

2

T64

68

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3089574	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

502698

1

T62

342

T63

17

T64

677

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1230028	1			T62	840		T63	54		T64	1545
values[0x0]	1132027	1			T62	806		T63	44		T64	1515
values[0x1]	1230217	1			T62	783		T63	52		T64	1583

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2371726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1220546

1

T62

838

T63

45

T64

1583

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55239	1			T62	29		T63	5		T64	81
valid_sources[0x01]	56236	1			T62	23		T64	68		T72	4
valid_sources[0x02]	55852	1			T62	50		T64	94		T72	1
valid_sources[0x03]	57307	1			T62	41		T63	7		T64	118
valid_sources[0x04]	55230	1			T62	29		T63	1		T64	69
valid_sources[0x05]	57010	1			T62	38		T63	2		T64	92
valid_sources[0x06]	55998	1			T62	33		T64	73		T72	5
valid_sources[0x07]	57084	1			T62	53		T63	9		T64	74
valid_sources[0x08]	55900	1			T62	55		T63	1		T64	124
valid_sources[0x09]	55115	1			T62	37		T64	38		T72	2
valid_sources[0x0a]	56783	1			T62	30		T64	81		T72	3
valid_sources[0x0b]	56859	1			T62	40		T63	2		T64	85
valid_sources[0x0c]	56374	1			T62	33		T64	105		T72	2
valid_sources[0x0d]	55294	1			T62	41		T63	4		T64	84
valid_sources[0x0e]	56718	1			T62	46		T63	4		T64	84
valid_sources[0x0f]	57200	1			T62	35		T64	107		T72	2
valid_sources[0x10]	56215	1			T62	40		T63	4		T64	101
valid_sources[0x11]	55567	1			T62	25		T63	5		T64	84
valid_sources[0x12]	57583	1			T62	49		T64	50		T72	2
valid_sources[0x13]	55643	1			T62	56		T64	78		T72	3
valid_sources[0x14]	55872	1			T62	36		T63	6		T64	60
valid_sources[0x15]	55994	1			T62	55		T63	8		T64	52
valid_sources[0x16]	56534	1			T62	19		T64	65		T72	3
valid_sources[0x17]	56723	1			T62	35		T63	2		T64	41
valid_sources[0x18]	56286	1			T62	42		T63	2		T64	123
valid_sources[0x19]	56565	1			T62	53		T64	117		T72	5
valid_sources[0x1a]	55626	1			T62	20		T63	1		T64	22
valid_sources[0x1b]	55584	1			T62	27		T64	43		T72	3
valid_sources[0x1c]	55151	1			T62	30		T64	149		T72	3
valid_sources[0x1d]	55900	1			T62	66		T64	58		T66	1
valid_sources[0x1e]	55832	1			T62	39		T63	2		T64	84
valid_sources[0x1f]	56612	1			T62	28		T64	98		T72	2
valid_sources[0x20]	55487	1			T62	28		T64	65		T72	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52863

1

T62

34

T63

3

T64

56

values[0x0]

all_enables

biggest_size

397061

1

T62

282

T63

13

T64

554

values[0x1]

all_enables

biggest_size

52774

1

T62

26

T63

1

T64

67

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2919805	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

461484

1

T62

327

T63

20

T64

627

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1144769	1			T62	869		T63	69		T64	1518
values[0x0]	1091421	1			T62	797		T63	61		T64	1476
values[0x1]	1145099	1			T62	850		T63	59		T64	1547

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2260526	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1120763

1

T62

828

T63

49

T64

1555

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52053	1			T62	37		T63	19		T64	82
valid_sources[0x01]	52883	1			T62	46		T63	2		T64	68
valid_sources[0x02]	52764	1			T62	45		T64	66		T72	1
valid_sources[0x03]	53243	1			T62	34		T63	3		T64	69
valid_sources[0x04]	52696	1			T62	37		T64	66		T72	2
valid_sources[0x05]	52405	1			T62	49		T63	5		T64	56
valid_sources[0x06]	53142	1			T62	45		T63	1		T64	75
valid_sources[0x07]	52641	1			T62	35		T64	56		T72	4
valid_sources[0x08]	53264	1			T62	41		T63	4		T64	73
valid_sources[0x09]	51717	1			T62	41		T63	6		T64	57
valid_sources[0x0a]	53272	1			T62	38		T63	3		T64	60
valid_sources[0x0b]	52794	1			T62	46		T64	70		T72	9
valid_sources[0x0c]	52694	1			T62	48		T64	77		T66	4
valid_sources[0x0d]	53154	1			T62	38		T64	70		T66	4
valid_sources[0x0e]	52015	1			T62	55		T63	8		T64	78
valid_sources[0x0f]	53870	1			T62	31		T63	7		T64	62
valid_sources[0x10]	51922	1			T62	36		T63	5		T64	59
valid_sources[0x11]	52570	1			T62	31		T63	3		T64	53
valid_sources[0x12]	52958	1			T62	37		T63	13		T64	74
valid_sources[0x13]	53487	1			T62	41		T64	63		T72	5
valid_sources[0x14]	53180	1			T62	41		T64	70		T66	4
valid_sources[0x15]	52600	1			T62	39		T63	2		T64	70
valid_sources[0x16]	53648	1			T62	42		T63	1		T64	71
valid_sources[0x17]	53333	1			T62	35		T64	60		T66	3
valid_sources[0x18]	53327	1			T62	42		T63	1		T64	79
valid_sources[0x19]	52877	1			T62	40		T64	77		T72	5
valid_sources[0x1a]	52916	1			T62	33		T64	76		T72	4
valid_sources[0x1b]	52538	1			T62	36		T63	16		T64	77
valid_sources[0x1c]	52730	1			T62	38		T63	3		T64	65
valid_sources[0x1d]	52184	1			T62	30		T63	1		T64	83
valid_sources[0x1e]	53702	1			T62	44		T63	3		T64	60
valid_sources[0x1f]	53499	1			T62	41		T64	69		T72	2
valid_sources[0x20]	52607	1			T62	43		T64	62		T105	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48652

1

T62

21

T63

3

T64

43

values[0x0]

all_enables

biggest_size

364417

1

T62

276

T63

16

T64

534

values[0x1]

all_enables

biggest_size

48415

1

T62

30

T63

1

T64

50