Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.25 94.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_i2c0 94.19 94.19
tb.dut.top_earlgrey.u_i2c1 94.22 94.22
tb.dut.top_earlgrey.u_i2c2 94.22 94.22



Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.19 94.19


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.19 94.19


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.09 90.68 88.59 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.22 94.22


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.22 94.22


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.09 90.68 88.59 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.22 94.22


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.22 94.22


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.09 90.68 88.59 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : i2c
TotalCoveredPercent
Totals 52 48 92.31
Total Bits 348 328 94.25
Total Bits 0->1 174 164 94.25
Total Bits 1->0 174 164 94.25

Ports 52 48 92.31
Port Bits 348 328 94.25
Port Bits 0->1 174 164 94.25
Port Bits 1->0 174 164 94.25

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T30 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T212,T213,T308 Yes T212,T213,T308 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T212,T213,T308 Yes T212,T213,T308 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T62,*T63,*T64 Yes T62,T63,T64 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T44,*T45,*T51 Yes T44,T45,T51 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T44,T45,T51 Yes T44,T45,T51 INPUT
tl_i.a_valid Yes Yes T212,T213,T70 Yes T212,T213,T70 INPUT
tl_o.a_ready Yes Yes T212,T213,T70 Yes T212,T213,T70 OUTPUT
tl_o.d_error Yes Yes T62,T63,T65 Yes T62,T63,T65 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T212,T213,T308 Yes T212,T213,T308 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T212,T213,T308 Yes T212,T213,T70 OUTPUT
tl_o.d_data[31:0] Yes Yes T212,T213,T308 Yes T212,T213,T70 OUTPUT
tl_o.d_sink Yes Yes T62,T63,T105 Yes T62,T63,T105 OUTPUT
tl_o.d_source[5:0] Yes Yes *T51,*T190,T62 Yes T51,T190,T62 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T62,T63,T65 Yes T62,T63,T65 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T212,*T213,*T308 Yes T212,T213,T308 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T212,T213,T70 Yes T212,T213,T70 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T286,T363,T70 Yes T286,T363,T70 INPUT
alert_rx_i[0].ping_n Yes Yes T88,T82,T197 Yes T88,T82,T197 INPUT
alert_rx_i[0].ping_p Yes Yes T88,T82,T197 Yes T88,T82,T197 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T286,T363,T70 Yes T286,T363,T70 OUTPUT
cio_scl_i Yes Yes T212,T213,T254 Yes T212,T213,T254 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T212,T213,T51 Yes T212,T213,T51 OUTPUT
cio_sda_i Yes Yes T212,T213,T254 Yes T212,T213,T254 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T212,T213,T254 Yes T212,T213,T254 OUTPUT
intr_fmt_threshold_o Yes Yes T212,T213,T308 Yes T212,T213,T308 OUTPUT
intr_rx_threshold_o Yes Yes T212,T213,T308 Yes T212,T213,T308 OUTPUT
intr_acq_threshold_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_rx_overflow_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_controller_halt_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_scl_interference_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_sda_interference_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_stretch_timeout_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_sda_unstable_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_cmd_complete_o Yes Yes T212,T213,T308 Yes T212,T213,T308 OUTPUT
intr_tx_stretch_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_tx_threshold_o Yes Yes T308,T51,T318 Yes T308,T51,T318 OUTPUT
intr_acq_stretch_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_unexp_stop_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_host_timeout_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0
TotalCoveredPercent
Totals 52 48 92.31
Total Bits 344 324 94.19
Total Bits 0->1 172 162 94.19
Total Bits 1->0 172 162 94.19

Ports 52 48 92.31
Port Bits 344 324 94.19
Port Bits 0->1 172 162 94.19
Port Bits 1->0 172 162 94.19

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T30 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T308,T254,T195 Yes T308,T254,T195 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T308,T254,T195 Yes T308,T254,T195 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T62,*T63,*T64 Yes T62,T63,T64 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T44,*T45,*T51 Yes T44,T45,T51 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T44,T45,T51 Yes T44,T45,T51 INPUT
tl_i.a_valid Yes Yes T70,T308,T254 Yes T70,T308,T254 INPUT
tl_o.a_ready Yes Yes T70,T308,T254 Yes T70,T308,T254 OUTPUT
tl_o.d_error Yes Yes T62,T63,T65 Yes T62,T63,T65 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T308,T254,T51 Yes T308,T254,T51 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T308,T254,T231 Yes T70,T308,T254 OUTPUT
tl_o.d_data[31:0] Yes Yes T308,T254,T231 Yes T70,T308,T254 OUTPUT
tl_o.d_sink Yes Yes T62,T63,T72 Yes T62,T63,T72 OUTPUT
tl_o.d_source[5:0] Yes Yes *T51,*T190,*T62 Yes T51,T190,T62 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T62,T63,T65 Yes T62,T63,T65 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T308,*T254,*T195 Yes T308,T254,T195 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T70,T308,T254 Yes T70,T308,T254 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T70,T88,T82 Yes T70,T88,T82 INPUT
alert_rx_i[0].ping_n Yes Yes T88,T82,T197 Yes T88,T82,T197 INPUT
alert_rx_i[0].ping_p Yes Yes T88,T82,T197 Yes T88,T82,T197 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T70,T88,T82 Yes T70,T88,T82 OUTPUT
cio_scl_i Yes Yes T254,T323,T324 Yes T254,T323,T324 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T323,T324,T325 Yes T323,T324,T325 OUTPUT
cio_sda_i Yes Yes T254,T323,T324 Yes T254,T323,T324 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T254,T51,T323 Yes T254,T51,T323 OUTPUT
intr_fmt_threshold_o Yes Yes T308,T51,T323 Yes T308,T51,T323 OUTPUT
intr_rx_threshold_o Yes Yes T308,T323,T324 Yes T308,T323,T324 OUTPUT
intr_acq_threshold_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_rx_overflow_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_controller_halt_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_scl_interference_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_sda_interference_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_stretch_timeout_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_sda_unstable_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_cmd_complete_o Yes Yes T308,T254,T323 Yes T308,T254,T323 OUTPUT
intr_tx_stretch_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_tx_threshold_o Yes Yes T308,T51,T318 Yes T308,T51,T318 OUTPUT
intr_acq_stretch_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_unexp_stop_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_host_timeout_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1
TotalCoveredPercent
Totals 52 48 92.31
Total Bits 346 326 94.22
Total Bits 0->1 173 163 94.22
Total Bits 1->0 173 163 94.22

Ports 52 48 92.31
Port Bits 346 326 94.22
Port Bits 0->1 173 163 94.22
Port Bits 1->0 173 163 94.22

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T30 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T308,T195,T51 Yes T308,T195,T51 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T308,T195,T51 Yes T308,T195,T51 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T62,*T63,*T64 Yes T62,T63,T64 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[18:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T44,*T45,*T51 Yes T44,T45,T51 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T44,T45,T51 Yes T44,T45,T51 INPUT
tl_i.a_valid Yes Yes T70,T308,T71 Yes T70,T308,T71 INPUT
tl_o.a_ready Yes Yes T70,T308,T71 Yes T70,T308,T71 OUTPUT
tl_o.d_error Yes Yes T62,T65,T72 Yes T62,T63,T65 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T308,T51,T316 Yes T308,T51,T316 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T308,T231,T195 Yes T70,T308,T71 OUTPUT
tl_o.d_data[31:0] Yes Yes T308,T231,T195 Yes T70,T308,T71 OUTPUT
tl_o.d_sink Yes Yes T62,T72,T66 Yes T62,T72,T66 OUTPUT
tl_o.d_source[5:0] Yes Yes *T51,*T190,T62 Yes T51,T190,T62 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T62,T65,T72 Yes T62,T65,T72 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T308,*T195,*T51 Yes T308,T195,T51 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T70,T308,T71 Yes T70,T308,T71 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T286,T363,T70 Yes T286,T363,T70 INPUT
alert_rx_i[0].ping_n Yes Yes T88,T82,T197 Yes T88,T82,T197 INPUT
alert_rx_i[0].ping_p Yes Yes T88,T82,T197 Yes T88,T82,T197 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T286,T363,T70 Yes T286,T363,T70 OUTPUT
cio_scl_i Yes Yes T316,T317,T326 Yes T316,T317,T326 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T51,T316,T317 Yes T51,T316,T317 OUTPUT
cio_sda_i Yes Yes T316,T317,T326 Yes T316,T317,T326 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T51,T316,T317 Yes T51,T316,T317 OUTPUT
intr_fmt_threshold_o Yes Yes T308,T51,T316 Yes T308,T51,T316 OUTPUT
intr_rx_threshold_o Yes Yes T308,T316,T317 Yes T308,T316,T317 OUTPUT
intr_acq_threshold_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_rx_overflow_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_controller_halt_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_scl_interference_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_sda_interference_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_stretch_timeout_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_sda_unstable_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_cmd_complete_o Yes Yes T308,T316,T317 Yes T308,T316,T317 OUTPUT
intr_tx_stretch_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_tx_threshold_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_acq_stretch_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_unexp_stop_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_host_timeout_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2
TotalCoveredPercent
Totals 52 48 92.31
Total Bits 346 326 94.22
Total Bits 0->1 173 163 94.22
Total Bits 1->0 173 163 94.22

Ports 52 48 92.31
Port Bits 346 326 94.22
Port Bits 0->1 173 163 94.22
Port Bits 1->0 173 163 94.22

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T30 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T212,T213,T308 Yes T212,T213,T308 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T212,T213,T308 Yes T212,T213,T308 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T62,*T63,*T64 Yes T62,T63,T64 INPUT
tl_i.a_address[16:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T44,*T45,*T51 Yes T44,T45,T51 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T62,T63,T64 Yes T62,T63,T64 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T44,T45,T51 Yes T44,T45,T51 INPUT
tl_i.a_valid Yes Yes T212,T213,T70 Yes T212,T213,T70 INPUT
tl_o.a_ready Yes Yes T212,T213,T70 Yes T212,T213,T70 OUTPUT
tl_o.d_error Yes Yes T62,T65,T105 Yes T62,T65,T105 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T212,T213,T308 Yes T212,T213,T308 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T212,T213,T308 Yes T212,T213,T70 OUTPUT
tl_o.d_data[31:0] Yes Yes T212,T213,T308 Yes T212,T213,T70 OUTPUT
tl_o.d_sink Yes Yes T62,T63,T105 Yes T62,T63,T105 OUTPUT
tl_o.d_source[5:0] Yes Yes *T51,*T190,T62 Yes T51,T190,T62 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T62,T63,T65 Yes T62,T63,T65 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T212,*T213,*T308 Yes T212,T213,T308 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T212,T213,T70 Yes T212,T213,T70 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T70,T88,T82 Yes T70,T88,T82 INPUT
alert_rx_i[0].ping_n Yes Yes T88,T82,T197 Yes T88,T82,T197 INPUT
alert_rx_i[0].ping_p Yes Yes T88,T82,T197 Yes T88,T82,T197 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T70,T88,T82 Yes T70,T88,T82 OUTPUT
cio_scl_i Yes Yes T212,T213,T364 Yes T212,T213,T364 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T212,T213,T364 Yes T212,T213,T364 OUTPUT
cio_sda_i Yes Yes T212,T213,T364 Yes T212,T213,T364 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T212,T213,T364 Yes T212,T213,T364 OUTPUT
intr_fmt_threshold_o Yes Yes T212,T213,T308 Yes T212,T213,T308 OUTPUT
intr_rx_threshold_o Yes Yes T212,T213,T308 Yes T212,T213,T308 OUTPUT
intr_acq_threshold_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_rx_overflow_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_controller_halt_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_scl_interference_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_sda_interference_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_stretch_timeout_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_sda_unstable_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_cmd_complete_o Yes Yes T212,T213,T308 Yes T212,T213,T308 OUTPUT
intr_tx_stretch_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_tx_threshold_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_acq_stretch_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_unexp_stop_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT
intr_host_timeout_o Yes Yes T308,T318,T319 Yes T308,T318,T319 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%