Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365837049	41134969	0	0
DepthKnown_A	365837049	365748752	0	0
RvalidKnown_A	365837049	365748752	0	0
WreadyKnown_A	365837049	365748752	0	0
gen_passthru_fifo.paramCheckPass	890	890	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	41134969	0	0
T1	153753	25626	0	0
T2	213681	20915	0	0
T3	108043	13902	0	0
T4	153358	232446	0	0
T5	208109	18795	0	0
T15	83943	9229	0	0
T30	651806	68753	0	0
T98	561363	87863	0	0
T112	63232	6206	0	0
T135	598387	53669	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	365748752	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	365748752	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	365748752	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	890	890	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365837049	32884371	0	0
DepthKnown_A	365837049	365748752	0	0
RvalidKnown_A	365837049	365748752	0	0
WreadyKnown_A	365837049	365748752	0	0
gen_passthru_fifo.paramCheckPass	890	890	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	32884371	0	0
T1	153753	17960	0	0
T2	213681	16366	0	0
T3	108043	10706	0	0
T4	153358	142124	0	0
T5	208109	14867	0	0
T15	83943	7116	0	0
T30	651806	51178	0	0
T98	561363	68613	0	0
T112	63232	4342	0	0
T135	598387	49761	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	365748752	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	365748752	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	365748752	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	890	890	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365837049	30307780	0	0
DepthKnown_A	365837049	365748752	0	0
RvalidKnown_A	365837049	365748752	0	0
WreadyKnown_A	365837049	365748752	0	0
gen_passthru_fifo.paramCheckPass	890	890	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	30307780	0	0
T1	153753	8986	0	0
T2	213681	15826	0	0
T3	108043	6745	0	0
T4	153358	439199	0	0
T5	208109	11401	0	0
T15	83943	5273	0	0
T30	651806	30680	0	0
T98	561363	160953	0	0
T112	63232	3545	0	0
T135	598387	74164	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	365748752	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	365748752	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	365748752	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	890	890	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365837049	25910481	0	0
DepthKnown_A	365837049	365748752	0	0
RvalidKnown_A	365837049	365748752	0	0
WreadyKnown_A	365837049	365748752	0	0
gen_passthru_fifo.paramCheckPass	890	890	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	25910481	0	0
T1	153753	8708	0	0
T2	213681	15609	0	0
T3	108043	6597	0	0
T4	153358	70677	0	0
T5	208109	11104	0	0
T15	83943	5150	0	0
T30	651806	29829	0	0
T98	561363	160712	0	0
T112	63232	3428	0	0
T135	598387	73963	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	365748752	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	365748752	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	365748752	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	890	890	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443603564	77253	0	0
DepthKnown_A	443603564	443503962	0	0
RvalidKnown_A	443603564	443503962	0	0
WreadyKnown_A	443603564	443503962	0	0
gen_passthru_fifo.paramCheckPass	2779	2779	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	77253	0	0
T1	153753	26	0	0
T2	213681	17	0	0
T3	108043	20	0	0
T4	153358	28	0	0
T5	208109	28	0	0
T15	83943	13	0	0
T30	651806	112	0	0
T98	561363	18	0	0
T112	63232	13	0	0
T135	598387	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2779	2779	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443603564	79899	0	0
DepthKnown_A	443603564	443503962	0	0
RvalidKnown_A	443603564	443503962	0	0
WreadyKnown_A	443603564	443503962	0	0
gen_passthru_fifo.paramCheckPass	2779	2779	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	79899	0	0
T1	153753	26	0	0
T2	213681	17	0	0
T3	108043	20	0	0
T4	153358	28	0	0
T5	208109	28	0	0
T15	83943	13	0	0
T30	651806	112	0	0
T98	561363	18	0	0
T112	63232	13	0	0
T135	598387	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2779	2779	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443603564	47477	0	0
DepthKnown_A	443603564	443503962	0	0
RvalidKnown_A	443603564	443503962	0	0
WreadyKnown_A	443603564	443503962	0	0
gen_passthru_fifo.paramCheckPass	2779	2779	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	47477	0	0
T1	153753	23	0	0
T2	213681	14	0	0
T3	108043	19	0	0
T4	153358	0	0	0
T5	208109	26	0	0
T15	83943	12	0	0
T30	651806	97	0	0
T98	561363	15	0	0
T112	63232	12	0	0
T135	598387	52	0	0
T187	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2779	2779	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443603564	47477	0	0
DepthKnown_A	443603564	443503962	0	0
RvalidKnown_A	443603564	443503962	0	0
WreadyKnown_A	443603564	443503962	0	0
gen_passthru_fifo.paramCheckPass	2779	2779	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	47477	0	0
T1	153753	23	0	0
T2	213681	14	0	0
T3	108043	19	0	0
T4	153358	0	0	0
T5	208109	26	0	0
T15	83943	12	0	0
T30	651806	97	0	0
T98	561363	15	0	0
T112	63232	12	0	0
T135	598387	52	0	0
T187	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2779	2779	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443603564	29776	0	0
DepthKnown_A	443603564	443503962	0	0
RvalidKnown_A	443603564	443503962	0	0
WreadyKnown_A	443603564	443503962	0	0
gen_passthru_fifo.paramCheckPass	2779	2779	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	29776	0	0
T1	153753	3	0	0
T2	213681	3	0	0
T3	108043	1	0	0
T4	153358	28	0	0
T5	208109	2	0	0
T15	83943	1	0	0
T30	651806	15	0	0
T98	561363	3	0	0
T112	63232	1	0	0
T135	598387	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2779	2779	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443603564	32422	0	0
DepthKnown_A	443603564	443503962	0	0
RvalidKnown_A	443603564	443503962	0	0
WreadyKnown_A	443603564	443503962	0	0
gen_passthru_fifo.paramCheckPass	2779	2779	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	32422	0	0
T1	153753	3	0	0
T2	213681	3	0	0
T3	108043	1	0	0
T4	153358	28	0	0
T5	208109	2	0	0
T15	83943	1	0	0
T30	651806	15	0	0
T98	561363	3	0	0
T112	63232	1	0	0
T135	598387	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603564	443503962	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2779	2779	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0