Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	90.68		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	90.68		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	90.68		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	90.68		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T44,*T45,*T51	Yes	T44,T45,T51	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T44,T45,T51	Yes	T44,T45,T51	INPUT
tl_i.a_valid	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	INPUT
tl_o.a_ready	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	OUTPUT
tl_o.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	OUTPUT
tl_o.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T135,*T187	Yes	T4,T135,T187	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T285,T70,T652	Yes	T285,T70,T652	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T285,T70,T652	Yes	T285,T70,T652	OUTPUT
cio_rx_i	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T135,T187,T283	Yes	T135,T187,T283	OUTPUT
intr_rx_watermark_o	Yes	Yes	T135,T187,T283	Yes	T135,T187,T283	OUTPUT
intr_tx_empty_o	Yes	Yes	T135,T187,T283	Yes	T135,T187,T283	OUTPUT
intr_rx_overflow_o	Yes	Yes	T135,T187,T283	Yes	T135,T187,T283	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_break_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_timeout_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T44,*T45,*T51	Yes	T44,T45,T51	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T44,T45,T51	Yes	T44,T45,T51	INPUT
tl_i.a_valid	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	INPUT
tl_o.a_ready	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	OUTPUT
tl_o.d_error	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	OUTPUT
tl_o.d_sink	Yes	Yes	T62,T63,T105	Yes	T62,T63,T105	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T62,*T105,*T72	Yes	T62,T63,T105	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T135,*T187	Yes	T4,T135,T187	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T82,T71	Yes	T70,T82,T71	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T82,T71	Yes	T70,T82,T71	OUTPUT
cio_rx_i	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T4,T135,T187	Yes	T4,T135,T187	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T135,T187,T283	Yes	T135,T187,T283	OUTPUT
intr_rx_watermark_o	Yes	Yes	T135,T187,T283	Yes	T135,T187,T283	OUTPUT
intr_tx_empty_o	Yes	Yes	T135,T187,T283	Yes	T135,T187,T283	OUTPUT
intr_rx_overflow_o	Yes	Yes	T135,T187,T283	Yes	T135,T187,T283	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_break_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_timeout_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T283,T208,T209	Yes	T283,T208,T209	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T283,T208,T209	Yes	T283,T208,T209	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T44,*T45,*T51	Yes	T44,T45,T51	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T44,T45,T51	Yes	T44,T45,T51	INPUT
tl_i.a_valid	Yes	Yes	T283,T208,T209	Yes	T283,T208,T209	INPUT
tl_o.a_ready	Yes	Yes	T283,T208,T209	Yes	T283,T208,T209	OUTPUT
tl_o.d_error	Yes	Yes	T62,T63,T65	Yes	T62,T63,T64	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T283,T208,T209	Yes	T283,T208,T209	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T283,T208,T209	Yes	T283,T208,T209	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T283,T208,T209	Yes	T283,T208,T209	OUTPUT
tl_o.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T62,*T105,*T72	Yes	T62,T63,T64	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T64	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T283,*T208,*T209	Yes	T283,T208,T209	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T283,T208,T209	Yes	T283,T208,T209	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T82,T71	Yes	T70,T82,T71	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T82,T71	Yes	T70,T82,T71	OUTPUT
cio_rx_i	Yes	Yes	T208,T209,T330	Yes	T10,T208,T209	INPUT
cio_tx_o	Yes	Yes	T208,T209,T330	Yes	T208,T209,T330	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T283,T208,T209	Yes	T283,T208,T209	OUTPUT
intr_rx_watermark_o	Yes	Yes	T283,T208,T209	Yes	T283,T208,T209	OUTPUT
intr_tx_empty_o	Yes	Yes	T283,T208,T209	Yes	T283,T208,T209	OUTPUT
intr_rx_overflow_o	Yes	Yes	T283,T208,T209	Yes	T283,T208,T209	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_break_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_timeout_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T283,T183,T315	Yes	T283,T183,T315	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T283,T183,T315	Yes	T283,T183,T315	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T44,*T45,*T51	Yes	T44,T45,T51	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T44,T45,T51	Yes	T44,T45,T51	INPUT
tl_i.a_valid	Yes	Yes	T283,T183,T315	Yes	T283,T183,T315	INPUT
tl_o.a_ready	Yes	Yes	T283,T183,T315	Yes	T283,T183,T315	OUTPUT
tl_o.d_error	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T283,T183,T315	Yes	T283,T183,T315	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T283,T183,T315	Yes	T283,T183,T315	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T283,T183,T315	Yes	T283,T183,T315	OUTPUT
tl_o.d_sink	Yes	Yes	T62,T63,T66	Yes	T62,T63,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T62,*T66,*T234	Yes	T62,T63,T66	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T283,*T183,*T315	Yes	T283,T183,T315	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T283,T183,T315	Yes	T283,T183,T315	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T285,T70,T652	Yes	T285,T70,T652	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T285,T70,T652	Yes	T285,T70,T652	OUTPUT
cio_rx_i	Yes	Yes	T183,T315,T322	Yes	T183,T315,T322	INPUT
cio_tx_o	Yes	Yes	T183,T315,T322	Yes	T183,T315,T322	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T283,T183,T315	Yes	T283,T183,T315	OUTPUT
intr_rx_watermark_o	Yes	Yes	T283,T183,T315	Yes	T283,T183,T315	OUTPUT
intr_tx_empty_o	Yes	Yes	T283,T183,T315	Yes	T283,T183,T315	OUTPUT
intr_rx_overflow_o	Yes	Yes	T283,T183,T315	Yes	T283,T183,T315	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_break_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_timeout_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T283,T307,T309	Yes	T283,T307,T309	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T283,T307,T309	Yes	T283,T307,T309	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T44,*T45,*T51	Yes	T44,T45,T51	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T44,T45,T51	Yes	T44,T45,T51	INPUT
tl_i.a_valid	Yes	Yes	T283,T307,T70	Yes	T283,T307,T70	INPUT
tl_o.a_ready	Yes	Yes	T283,T307,T70	Yes	T283,T307,T70	OUTPUT
tl_o.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T283,T307,T309	Yes	T283,T307,T309	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T283,T307,T231	Yes	T283,T307,T70	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T283,T307,T231	Yes	T283,T307,T70	OUTPUT
tl_o.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T283,*T307,*T309	Yes	T283,T307,T309	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T283,T307,T70	Yes	T283,T307,T70	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T82,T71	Yes	T70,T82,T71	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T82,T71	Yes	T70,T82,T71	OUTPUT
cio_rx_i	Yes	Yes	T309,T177,T331	Yes	T309,T177,T331	INPUT
cio_tx_o	Yes	Yes	T309,T177,T331	Yes	T309,T177,T331	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T283,T307,T309	Yes	T283,T307,T309	OUTPUT
intr_rx_watermark_o	Yes	Yes	T283,T307,T309	Yes	T283,T307,T309	OUTPUT
intr_tx_empty_o	Yes	Yes	T283,T307,T309	Yes	T283,T307,T309	OUTPUT
intr_rx_overflow_o	Yes	Yes	T283,T307,T309	Yes	T283,T307,T309	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_break_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_timeout_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T283,T307,T327	Yes	T283,T307,T327	OUTPUT

*Tests covering at least one bit in the range