Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	90.68		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T105,T66,T234	Yes	T105,T66,T234	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T196,T85,T215	Yes	T196,T85,T215	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T196,T227,T85	Yes	T196,T227,T85	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T44,T45,T51	Yes	T44,T45,T51	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T45,T54,T65	Yes	T45,T54,T65	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T45,T54,T62	Yes	T45,T54,T62	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T30,T86,T216	Yes	T30,T86,T216	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T44,*T45,*T46	Yes	T44,T45,T46	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T51,T54,T62	Yes	T51,T54,T62	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T51,T54,T62	Yes	T51,T54,T62	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T51,T54,T62	Yes	T51,T54,T62	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T51,T54,T62	Yes	T51,T54,T62	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T51,T54,T62	Yes	T51,T54,T62	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T51,*T54,T62	Yes	T51,T54,T62	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T62,T64,T65	Yes	T62,T64,T65	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T51,T54,T62	Yes	T51,T54,T62	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T51,T54,T62	Yes	T51,T54,T62	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T64,T65	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T51,T54,T62	Yes	T51,T54,T62	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T51,T54,T62	Yes	T51,T54,T62	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T51,T54,T62	Yes	T51,T54,T62	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T62,T64,T72	Yes	T62,T64,T72	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T51,*T54,T62	Yes	T51,T54,T62	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T64,T65	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T51,*T54,*T62	Yes	T51,T54,T62	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T51,T54,T62	Yes	T51,T54,T62	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T51,T73,T74	Yes	T51,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T51,T73,T74	Yes	T51,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T51,T73,T74	Yes	T51,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T51,T73,T74	Yes	T51,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T51,T73,T74	Yes	T51,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T51,T73,T74	Yes	T51,T73,T74	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T5,T30	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T51,T73,T74	Yes	T51,T73,T74	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T4,T5,T30	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T4,T5,T30	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T51,T73,T74	Yes	T51,T73,T74	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T44,T94,T45	Yes	T44,T94,T45	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T70,T71,T51	Yes	T70,T71,T51	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T70,T292,T263	Yes	T70,T292,T263	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T70,T292,T263	Yes	T70,T292,T263	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T70,T71,T51	Yes	T70,T71,T51	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T70,T292,T263	Yes	T70,T292,T263	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T51,*T54,*T62	Yes	T51,T54,T62	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T70,T292,T263	Yes	T70,T292,T263	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T70,T292,T263	Yes	T70,T292,T263	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T292,T263,T264	Yes	T292,T263,T264	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T51,T54,T62	Yes	T70,T71,T51	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T292,T263,T51	Yes	T70,T292,T263	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T62,T63,T105	Yes	T62,T63,T105	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T51,*T54,T62	Yes	T51,T54,T62	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T263,*T386,*T273	Yes	T292,T263,T386	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T70,T292,T263	Yes	T70,T292,T263	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T44,*T45,*T51	Yes	T44,T45,T51	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T44,T45,T51	Yes	T44,T45,T51	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T87,T284,T329	Yes	T87,T284,T329	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T44,*T45,*T51	Yes	T44,T45,T51	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T10,T107,T70	Yes	T10,T107,T70	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T10,T107,T70	Yes	T10,T107,T70	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T10,T107,T70	Yes	T10,T107,T70	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T10,T107,T70	Yes	T10,T107,T70	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T10,T107,T70	Yes	T10,T107,T70	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T10,T107,T70	Yes	T10,T107,T70	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T190,*T62,*T63	Yes	T190,T62,T63	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T198,T200,T201	Yes	T198,T200,T201	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T10,T107,T70	Yes	T10,T107,T70	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T10,T107,T70	Yes	T10,T107,T70	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T107,T195	Yes	T10,T107,T195	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T107,T231	Yes	T10,T107,T70	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T107,T195	Yes	T10,T107,T195	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T190,*T62,*T63	Yes	T190,T62,T63	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T107,*T195	Yes	T10,T107,T195	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T10,T107,T70	Yes	T10,T107,T70	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T107,T70,T71	Yes	T107,T70,T71	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T107,T70,T71	Yes	T107,T70,T71	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T107,T70,T71	Yes	T107,T70,T71	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T107,T70,T71	Yes	T107,T70,T71	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T107,T70,T71	Yes	T107,T70,T71	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T107,T70,T71	Yes	T107,T70,T71	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T190,*T62,*T63	Yes	T190,T62,T63	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T107,T70,T71	Yes	T107,T70,T71	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T107,T70,T71	Yes	T107,T70,T71	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T107,T32,T195	Yes	T107,T32,T195	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T107,T32,T195	Yes	T107,T70,T71	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T107,T32,T195	Yes	T107,T32,T195	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T62,T63,T105	Yes	T62,T63,T72	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T190,*T62,*T105	Yes	T190,T62,T63	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T107,*T32,*T195	Yes	T107,T32,T195	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T107,T70,T71	Yes	T107,T70,T71	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T15,T186,T283	Yes	T15,T186,T283	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T186,T283,T16	Yes	T186,T283,T16	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T15,T186,T283	Yes	T15,T186,T283	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T15,T186,T283	Yes	T15,T186,T283	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T283,T16,T49	Yes	T283,T16,T49	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T15,T186,T283	Yes	T15,T186,T283	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T15,T186,T283	Yes	T15,T186,T283	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T15,T186,T283	Yes	T15,T186,T283	INPUT
tl_usbdev_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T186,T283,T307	Yes	T15,T186,T283	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T186,T283	Yes	T186,T283,T307	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T15,T186,T283	Yes	T186,T283,T307	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T62,*T64,*T72	Yes	T62,T63,T64	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T186,*T283,*T16	Yes	T186,T283,T307	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T15,T186,T283	Yes	T15,T186,T283	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T62,T65,T105	Yes	T62,T65,T105	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T5,T30	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T4,T5,T30	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T62,T72,T66	Yes	T62,T63,T72	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T62,T65,T72	Yes	T62,T65,T72	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T51,T190,T62	Yes	T51,T190,T62	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T51,T190,T62	Yes	T51,T190,T62	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T51,T190,T62	Yes	T51,T190,T62	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T51,T190,T62	Yes	T51,T190,T62	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T51,T190,T62	Yes	T51,T190,T62	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T51,*T190,T62	Yes	T51,T190,T62	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T51,T190,T62	Yes	T51,T190,T62	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T51,T190,T62	Yes	T51,T190,T62	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T51,T190,T62	Yes	T51,T190,T62	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T51,T190,T62	Yes	T51,T190,T62	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T51,T190,T62	Yes	T51,T190,T62	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T51,*T190,T62	Yes	T51,T190,T62	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T51,T190,T62	Yes	T51,T190,T62	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T5,T30	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T669	Yes	T3,T4,T669	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T669	Yes	T3,T4,T669	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T31	Yes	T3,T4,T31	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T3,T4,T669	Yes	T3,T4,T669	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T3,T4,T31	Yes	T3,T4,T31	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T3,T669,T670	Yes	T3,T669,T670	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T3,T4,T31	Yes	T3,T4,T31	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T3,T4,T31	Yes	T3,T4,T31	INPUT
tl_hmac_i.d_error	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T31	Yes	T3,T4,T31	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T31	Yes	T3,T4,T31	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T3,T4,T669	Yes	T3,T4,T669	INPUT
tl_hmac_i.d_sink	Yes	Yes	T62,T63,T105	Yes	T62,T63,T105	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T669	Yes	T3,T4,T669	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T3,T4,T31	Yes	T3,T4,T31	INPUT
tl_kmac_o.d_ready	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T97,T159,T189	Yes	T97,T159,T189	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T97,T61	Yes	T31,T97,T61	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T31,T97,T61	Yes	T31,T97,T61	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T159,T189,T67	Yes	T159,T189,T67	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T31,T97,T61	Yes	T31,T97,T61	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T159,T189,T155	Yes	T159,T189,T155	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T31,T97,T61	Yes	T31,T97,T61	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T31,T97,T61	Yes	T31,T97,T61	INPUT
tl_kmac_i.d_error	Yes	Yes	T62,T63,T65	Yes	T62,T63,T64	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T31,T97,T61	Yes	T31,T97,T61	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T97,T61	Yes	T31,T97,T61	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T97,T61,T159	Yes	T61,T159,T189	INPUT
tl_kmac_i.d_sink	Yes	Yes	T62,T63,T105	Yes	T62,T63,T64	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T97,*T61,*T159	Yes	T61,T159,T189	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T31,T97,T61	Yes	T31,T97,T61	INPUT
tl_aes_o.d_ready	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T113,T97,T668	Yes	T113,T97,T668	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T113,T97,T668	Yes	T113,T97,T668	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T113,T31,T97	Yes	T113,T31,T97	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T113,T97,T668	Yes	T113,T97,T668	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T113,T31,T97	Yes	T113,T31,T97	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T54,*T62,*T63	Yes	T54,T62,T63	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T113,T31,T97	Yes	T113,T31,T97	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T113,T31,T97	Yes	T113,T31,T97	INPUT
tl_aes_i.d_error	Yes	Yes	T62,T65,T105	Yes	T62,T65,T105	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T113,T31,T97	Yes	T113,T31,T97	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T113,T97,T668	Yes	T113,T97,T668	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T113,T31,T97	Yes	T113,T31,T97	INPUT
tl_aes_i.d_sink	Yes	Yes	T62,T63,T105	Yes	T62,T63,T105	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T54,*T62,*T63	Yes	T54,T62,T63	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T65,T105	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T113,*T31,*T97	Yes	T113,T31,T97	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T113,T31,T97	Yes	T113,T31,T97	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T98,T161,T97	Yes	T98,T161,T97	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T98,T5	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T98,T5	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T98,*T161,*T97	Yes	T98,T161,T97	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T51,*T54,*T190	Yes	T51,T54,T190	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T98,T5	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T4,T98,T5	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T62,T63,T66	Yes	T62,T63,T72	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T51,*T54,*T190	Yes	T51,T54,T190	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T98,*T97,*T67	Yes	T98,T97,T67	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T98,T5	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T4,T98,T5	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T62,T63,T105	Yes	T62,T63,T72	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T65	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T98,*T97,*T67	Yes	T98,T97,T67	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T4,T98,T5	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	INPUT
tl_edn1_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	INPUT
tl_edn1_i.d_sink	Yes	Yes	T62,T64,T105	Yes	T62,T63,T64	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T64,T65	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T98,*T97,*T67	Yes	T98,T97,T67	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T98,T97,T67	Yes	T98,T97,T67	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T2,T98,T30	Yes	T2,T98,T30	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T98	Yes	T1,T2,T98	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T98	Yes	T1,T2,T98	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T2,T98	Yes	T1,T2,T98	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T2,T98	Yes	T1,T2,T98	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T190,*T62,*T63	Yes	T190,T62,T63	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T62,T65,T105	Yes	T62,T65,T105	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T2,T98	Yes	T1,T2,T98	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T2,T98	Yes	T1,T2,T98	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T62,T65,T105	Yes	T62,T65,T105	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T2,T98,T30	Yes	T2,T98,T30	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T98	Yes	T1,T2,T98	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T2,T98	Yes	T1,T2,T98	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T62,T63,T105	Yes	T62,T63,T105	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T190,*T62,*T105	Yes	T190,T62,T63	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T62,T65,T105	Yes	T62,T65,T105	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T98	Yes	T1,T2,T98	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T2,T98	Yes	T1,T2,T98	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T98,T5	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T98,T42,T43	Yes	T98,T42,T43	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T98,T31,T42	Yes	T98,T31,T42	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T98,T31,T42	Yes	T98,T31,T42	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T98,T42,T43	Yes	T98,T42,T43	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T98,T31,T42	Yes	T98,T31,T42	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T44,*T45,*T259	Yes	T44,T45,T259	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T62,T64,T65	Yes	T62,T64,T65	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T98,T31,T42	Yes	T98,T31,T42	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T98,T31,T42	Yes	T98,T31,T42	INPUT
tl_otbn_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T98,T42,T43	Yes	T98,T42,T43	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T98,T42,T43	Yes	T98,T42,T43	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T98,T42,T43	Yes	T98,T42,T43	INPUT
tl_otbn_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T44,*T45,*T259	Yes	T44,T45,T259	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T62,T64,T65	Yes	T62,T64,T65	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T98,*T42,*T43	Yes	T98,T42,T43	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T98,T42,T43	Yes	T98,T42,T43	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T5,T30	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T97,T42,T61	Yes	T97,T42,T61	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T97,T42,T61	Yes	T97,T42,T61	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T97,T42,T61	Yes	T97,T42,T61	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T97,T61,T43	Yes	T97,T61,T43	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T97,T42,T61	Yes	T97,T42,T61	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T97,T42,T61	Yes	T97,T42,T61	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T97,T42,T61	Yes	T97,T42,T61	INPUT
tl_keymgr_i.d_error	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T97,T61,T76	Yes	T97,T61,T76	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T97,T42,T61	Yes	T97,T42,T61	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T97,T42,T61	Yes	T97,T42,T61	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T51,*T190,*T62	Yes	T51,T190,T62	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T97,*T42,*T61	Yes	T97,T42,T61	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T97,T42,T61	Yes	T97,T42,T61	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T51,*T54,*T62	Yes	T51,T54,T62	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T51,T54,T62	Yes	T51,T54,T62	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T62,T64,T105	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T51,*T54,*T62	Yes	T51,T54,T62	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T5,T112	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T4,T42,T43	Yes	T4,T42,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T112,T42	Yes	T4,T112,T42	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T112,T42	Yes	T4,T112,T42	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T4,T42,T43	Yes	T4,T42,T43	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T4,T112,T42	Yes	T4,T112,T42	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T190,*T62,*T63	Yes	T190,T62,T63	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T62,T64,T65	Yes	T62,T64,T65	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T4,T112,T42	Yes	T4,T112,T42	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T4,T112,T42	Yes	T4,T112,T42	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T62,T64,T65	Yes	T62,T64,T65	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T100,T101,T296	Yes	T100,T101,T296	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T114,T115	Yes	T4,T42,T43	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T4,T114,T115	Yes	T4,T42,T43	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T62,T64,T105	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T190,*T62,*T64	Yes	T190,T62,T63	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T114,*T115,*T275	Yes	T112,T114,T115	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T4,T112,T42	Yes	T4,T112,T42	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T5,T30	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range