Module Definition
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Module : tlul_socket_1n
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.64 94.64 93.18 94.74 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket 95.64 94.64 93.18 94.74 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.64 94.64 93.18 94.74 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.72 96.25 94.64 96.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.84 100.00 99.36 100.00 100.00 u_reg_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
fifo_h 100.00 100.00 100.00 100.00 100.00
gen_dfifo[0].fifo_d 100.00 100.00 100.00 100.00 100.00
gen_dfifo[1].fifo_d 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : tlul_socket_1n
Line No.TotalCoveredPercent
TOTAL565394.64
CONT_ASSIGN11211100.00
CONT_ASSIGN11311100.00
ALWAYS11699100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
ALWAYS18066100.00
CONT_ASSIGN18911100.00
ALWAYS19244100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN199100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN202100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN252100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
112 1 1
113 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
121 1 1
==> MISSING_ELSE
123 1 1
124 1 1
125 1 1
MISSING_ELSE
132 1 1
145 1 1
155 2 2
157 2 2
158 2 2
159 2 2
160 2 2
161 2 2
162 2 2
163 2 2
164 2 2
167 2 2
171 2 2
180 1 1
181 1 1
183 2 2
MISSING_ELSE
185 2 2
MISSING_ELSE
189 1 1
192 1 1
193 1 1
194 2 2
MISSING_ELSE
197 1 1
198 1 1
199 0 1
200 1 1
201 1 1
202 0 1
203 1 1
204 1 1
205 1 1
252 0 1


Cond Coverage for Module : tlul_socket_1n
TotalCoveredPercent
Conditions444193.18
Logical444193.18
Non-Logical00
Event00

 LINE       112
 EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
             -------1------   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT181,T376,T377
11CoveredT1,T2,T3

 LINE       113
 EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT181,T374,T378
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
             -------------1-------------   --------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       132
 SUB-EXPRESSION (num_req_outstanding != '0)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
                --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 1'(0)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 1'(0))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 1'(1)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 1'(1))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 EXPRESSION (dev_select_t == 1'(idx))
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       189
 EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT181,T376,T377
11CoveredT1,T2,T3

 LINE       194
 EXPRESSION (dev_select_outstanding == 1'(idx))
            -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : tlul_socket_1n
Line No.TotalCoveredPercent
Branches 19 18 94.74
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
IF 116 5 4 80.00
IF 183 2 2 100.00
IF 185 2 2 100.00
IF 194 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 164 (gen_u_o[0].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[0].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[1].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[1].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 116 if ((!rst_ni)) -2-: 119 if (accept_t_req) -3-: 120 if ((!accept_t_rsp)) -4-: 124 if (accept_t_rsp)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 1 - Covered T1,T2,T3
0 1 0 - Not Covered
0 0 - 1 Covered T1,T2,T3
0 0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 183 if ((dev_select_t == 1'(idx)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 185 if (hold_all_requests)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 194 if ((dev_select_outstanding == 1'(idx)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_socket_1n
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NotOverflowed_A 443603564 443503962 0 0
maxN 2779 2779 0 0


NotOverflowed_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 443603564 443503962 0 0
T1 153753 153698 0 0
T2 213681 213623 0 0
T3 108043 107988 0 0
T4 153358 153317 0 0
T5 208109 207944 0 0
T15 83943 83885 0 0
T30 651806 651436 0 0
T98 561363 561305 0 0
T112 63232 63174 0 0
T135 598387 598329 0 0

maxN
NameAttemptsReal SuccessesFailuresIncomplete
Total 2779 2779 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T30 1 1 0 0
T98 1 1 0 0
T112 1 1 0 0
T135 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket
Line No.TotalCoveredPercent
TOTAL565394.64
CONT_ASSIGN11211100.00
CONT_ASSIGN11311100.00
ALWAYS11699100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
ALWAYS18066100.00
CONT_ASSIGN18911100.00
ALWAYS19244100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN199100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN202100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN252100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
112 1 1
113 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
121 1 1
==> MISSING_ELSE
123 1 1
124 1 1
125 1 1
MISSING_ELSE
132 1 1
145 1 1
155 2 2
157 2 2
158 2 2
159 2 2
160 2 2
161 2 2
162 2 2
163 2 2
164 2 2
167 2 2
171 2 2
180 1 1
181 1 1
183 2 2
MISSING_ELSE
185 2 2
MISSING_ELSE
189 1 1
192 1 1
193 1 1
194 2 2
MISSING_ELSE
197 1 1
198 1 1
199 0 1
200 1 1
201 1 1
202 0 1
203 1 1
204 1 1
205 1 1
252 0 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket
TotalCoveredPercent
Conditions444193.18
Logical444193.18
Non-Logical00
Event00

 LINE       112
 EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
             -------1------   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT181,T376,T377
11CoveredT1,T2,T3

 LINE       113
 EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT181,T374,T378
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
             -------------1-------------   --------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       132
 SUB-EXPRESSION (num_req_outstanding != '0)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
                --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 1'(0)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 1'(0))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 1'(1)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 1'(1))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 EXPRESSION (dev_select_t == 1'(idx))
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       189
 EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT181,T376,T377
11CoveredT1,T2,T3

 LINE       194
 EXPRESSION (dev_select_outstanding == 1'(idx))
            -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket
Line No.TotalCoveredPercent
Branches 19 18 94.74
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
IF 116 5 4 80.00
IF 183 2 2 100.00
IF 185 2 2 100.00
IF 194 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 164 (gen_u_o[0].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[0].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[1].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[1].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 116 if ((!rst_ni)) -2-: 119 if (accept_t_req) -3-: 120 if ((!accept_t_rsp)) -4-: 124 if (accept_t_rsp)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 1 - Covered T1,T2,T3
0 1 0 - Not Covered
0 0 - 1 Covered T1,T2,T3
0 0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 183 if ((dev_select_t == 1'(idx)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 185 if (hold_all_requests)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 194 if ((dev_select_outstanding == 1'(idx)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NotOverflowed_A 443603564 443503962 0 0
maxN 2779 2779 0 0


NotOverflowed_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 443603564 443503962 0 0
T1 153753 153698 0 0
T2 213681 213623 0 0
T3 108043 107988 0 0
T4 153358 153317 0 0
T5 208109 207944 0 0
T15 83943 83885 0 0
T30 651806 651436 0 0
T98 561363 561305 0 0
T112 63232 63174 0 0
T135 598387 598329 0 0

maxN
NameAttemptsReal SuccessesFailuresIncomplete
Total 2779 2779 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T30 1 1 0 0
T98 1 1 0 0
T112 1 1 0 0
T135 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%