Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T117,T51,T289
0	1	Covered	T117,T289,T290
1	0	Covered	T54

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T117,T289,T54
1	Covered	T117,T51,T289

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T117,T289,T54
1	Covered	T117,T51,T289

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T117,T289,T290
1	1	Covered	T117,T289,T54

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T117,T51,T289
1	0	Covered	T117,T289,T54
1	1	Covered	T117,T289,T290

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T117,T289,T54

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T117,T51,T289
0	Covered	T117,T289,T54

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T117,T51,T289
0	Covered	T117,T289,T54

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	731674098	710628412	0	0
CheckNGreaterZero_A	1780	1780	0	0
GntImpliesReady_A	731674098	5377	0	0
GntImpliesValid_A	731674098	5377	0	0
GrantKnown_A	731674098	710628412	0	0
IdxKnown_A	731674098	710628412	0	0
IndexIsCorrect_A	731674098	5377	0	0
NoReadyValidNoGrant_A	731674098	0	0	0
Priority_A	731674098	5377	0	0
ReadyAndValidImplyGrant_A	731674098	5377	0	0
ReqAndReadyImplyGrant_A	731674098	5377	0	0
ReqImpliesValid_A	731674098	5377	0	0
ValidKnown_A	731674098	710628412	0	0
gen_data_port_assertion.DataFlow_A	731674098	5377	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731674098	710628412	0	0
T1	307506	307396	0	0
T2	427362	427246	0	0
T3	216086	215976	0	0
T4	306716	306634	0	0
T5	416218	415888	0	0
T15	167886	167770	0	0
T30	1303612	1302872	0	0
T98	1122726	1122610	0	0
T112	126464	126348	0	0
T135	1196774	1196658	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1780	1780	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T15	2	2	0	0
T30	2	2	0	0
T98	2	2	0	0
T112	2	2	0	0
T135	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731674098	5377	0	0
T18	362558	0	0	0
T117	208158	1790	0	0
T118	151476	0	0	0
T134	309118	0	0	0
T263	565622	0	0	0
T289	0	1786	0	0
T290	0	1801	0	0
T291	635938	0	0	0
T292	121882	0	0	0
T293	159566	0	0	0
T294	397442	0	0	0
T295	200458	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731674098	5377	0	0
T18	362558	0	0	0
T117	208158	1790	0	0
T118	151476	0	0	0
T134	309118	0	0	0
T263	565622	0	0	0
T289	0	1786	0	0
T290	0	1801	0	0
T291	635938	0	0	0
T292	121882	0	0	0
T293	159566	0	0	0
T294	397442	0	0	0
T295	200458	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731674098	710628412	0	0
T1	307506	307396	0	0
T2	427362	427246	0	0
T3	216086	215976	0	0
T4	306716	306634	0	0
T5	416218	415888	0	0
T15	167886	167770	0	0
T30	1303612	1302872	0	0
T98	1122726	1122610	0	0
T112	126464	126348	0	0
T135	1196774	1196658	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731674098	710628412	0	0
T1	307506	307396	0	0
T2	427362	427246	0	0
T3	216086	215976	0	0
T4	306716	306634	0	0
T5	416218	415888	0	0
T15	167886	167770	0	0
T30	1303612	1302872	0	0
T98	1122726	1122610	0	0
T112	126464	126348	0	0
T135	1196774	1196658	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731674098	5377	0	0
T18	362558	0	0	0
T117	208158	1790	0	0
T118	151476	0	0	0
T134	309118	0	0	0
T263	565622	0	0	0
T289	0	1786	0	0
T290	0	1801	0	0
T291	635938	0	0	0
T292	121882	0	0	0
T293	159566	0	0	0
T294	397442	0	0	0
T295	200458	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731674098	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731674098	5377	0	0
T18	362558	0	0	0
T117	208158	1790	0	0
T118	151476	0	0	0
T134	309118	0	0	0
T263	565622	0	0	0
T289	0	1786	0	0
T290	0	1801	0	0
T291	635938	0	0	0
T292	121882	0	0	0
T293	159566	0	0	0
T294	397442	0	0	0
T295	200458	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731674098	5377	0	0
T18	362558	0	0	0
T117	208158	1790	0	0
T118	151476	0	0	0
T134	309118	0	0	0
T263	565622	0	0	0
T289	0	1786	0	0
T290	0	1801	0	0
T291	635938	0	0	0
T292	121882	0	0	0
T293	159566	0	0	0
T294	397442	0	0	0
T295	200458	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731674098	5377	0	0
T18	362558	0	0	0
T117	208158	1790	0	0
T118	151476	0	0	0
T134	309118	0	0	0
T263	565622	0	0	0
T289	0	1786	0	0
T290	0	1801	0	0
T291	635938	0	0	0
T292	121882	0	0	0
T293	159566	0	0	0
T294	397442	0	0	0
T295	200458	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731674098	5377	0	0
T18	362558	0	0	0
T117	208158	1790	0	0
T118	151476	0	0	0
T134	309118	0	0	0
T263	565622	0	0	0
T289	0	1786	0	0
T290	0	1801	0	0
T291	635938	0	0	0
T292	121882	0	0	0
T293	159566	0	0	0
T294	397442	0	0	0
T295	200458	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731674098	710628412	0	0
T1	307506	307396	0	0
T2	427362	427246	0	0
T3	216086	215976	0	0
T4	306716	306634	0	0
T5	416218	415888	0	0
T15	167886	167770	0	0
T30	1303612	1302872	0	0
T98	1122726	1122610	0	0
T112	126464	126348	0	0
T135	1196774	1196658	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731674098	5377	0	0
T18	362558	0	0	0
T117	208158	1790	0	0
T118	151476	0	0	0
T134	309118	0	0	0
T263	565622	0	0	0
T289	0	1786	0	0
T290	0	1801	0	0
T291	635938	0	0	0
T292	121882	0	0	0
T293	159566	0	0	0
T294	397442	0	0	0
T295	200458	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T117,T51,T289
0	1	Covered	T117,T289,T290
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T117,T289,T290
1	Covered	T117,T51,T289

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T117,T289,T290
1	Covered	T117,T51,T289

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T117,T289,T290
1	1	Covered	T117,T289,T290

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T117,T51,T289
1	0	Covered	T117,T289,T290
1	1	Covered	T117,T289,T290

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T117,T289,T290

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T117,T51,T289
0	Covered	T117,T289,T290

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T117,T51,T289
0	Covered	T117,T289,T290

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	365837049	355314206	0	0
CheckNGreaterZero_A	890	890	0	0
GntImpliesReady_A	365837049	4387	0	0
GntImpliesValid_A	365837049	4387	0	0
GrantKnown_A	365837049	355314206	0	0
IdxKnown_A	365837049	355314206	0	0
IndexIsCorrect_A	365837049	4387	0	0
NoReadyValidNoGrant_A	365837049	0	0	0
Priority_A	365837049	4387	0	0
ReadyAndValidImplyGrant_A	365837049	4387	0	0
ReqAndReadyImplyGrant_A	365837049	4387	0	0
ReqImpliesValid_A	365837049	4387	0	0
ValidKnown_A	365837049	355314206	0	0
gen_data_port_assertion.DataFlow_A	365837049	4387	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	355314206	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	890	890	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	4387	0	0
T18	181279	0	0	0
T117	104079	1460	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	1456	0	0
T290	0	1471	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	4387	0	0
T18	181279	0	0	0
T117	104079	1460	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	1456	0	0
T290	0	1471	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	355314206	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	355314206	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	4387	0	0
T18	181279	0	0	0
T117	104079	1460	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	1456	0	0
T290	0	1471	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	4387	0	0
T18	181279	0	0	0
T117	104079	1460	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	1456	0	0
T290	0	1471	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	4387	0	0
T18	181279	0	0	0
T117	104079	1460	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	1456	0	0
T290	0	1471	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	4387	0	0
T18	181279	0	0	0
T117	104079	1460	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	1456	0	0
T290	0	1471	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	4387	0	0
T18	181279	0	0	0
T117	104079	1460	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	1456	0	0
T290	0	1471	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	355314206	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	4387	0	0
T18	181279	0	0	0
T117	104079	1460	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	1456	0	0
T290	0	1471	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T117,T51,T289
0	1	Covered	T117,T289,T290
1	0	Covered	T54

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T117,T289,T54
1	Covered	T117,T51,T289

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T117,T289,T54
1	Covered	T117,T51,T289

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T117,T289,T290
1	1	Covered	T117,T289,T54

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T117,T51,T289
1	0	Covered	T117,T289,T54
1	1	Covered	T117,T289,T290

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T117,T289,T54

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T117,T51,T289
0	Covered	T117,T289,T54

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T117,T51,T289
0	Covered	T117,T289,T54

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	365837049	355314206	0	0
CheckNGreaterZero_A	890	890	0	0
GntImpliesReady_A	365837049	990	0	0
GntImpliesValid_A	365837049	990	0	0
GrantKnown_A	365837049	355314206	0	0
IdxKnown_A	365837049	355314206	0	0
IndexIsCorrect_A	365837049	990	0	0
NoReadyValidNoGrant_A	365837049	0	0	0
Priority_A	365837049	990	0	0
ReadyAndValidImplyGrant_A	365837049	990	0	0
ReqAndReadyImplyGrant_A	365837049	990	0	0
ReqImpliesValid_A	365837049	990	0	0
ValidKnown_A	365837049	355314206	0	0
gen_data_port_assertion.DataFlow_A	365837049	990	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	355314206	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	890	890	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	990	0	0
T18	181279	0	0	0
T117	104079	330	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	330	0	0
T290	0	330	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	990	0	0
T18	181279	0	0	0
T117	104079	330	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	330	0	0
T290	0	330	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	355314206	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	355314206	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	990	0	0
T18	181279	0	0	0
T117	104079	330	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	330	0	0
T290	0	330	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	990	0	0
T18	181279	0	0	0
T117	104079	330	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	330	0	0
T290	0	330	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	990	0	0
T18	181279	0	0	0
T117	104079	330	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	330	0	0
T290	0	330	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	990	0	0
T18	181279	0	0	0
T117	104079	330	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	330	0	0
T290	0	330	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	990	0	0
T18	181279	0	0	0
T117	104079	330	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	330	0	0
T290	0	330	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	355314206	0	0
T1	153753	153698	0	0
T2	213681	213623	0	0
T3	108043	107988	0	0
T4	153358	153317	0	0
T5	208109	207944	0	0
T15	83943	83885	0	0
T30	651806	651436	0	0
T98	561363	561305	0	0
T112	63232	63174	0	0
T135	598387	598329	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365837049	990	0	0
T18	181279	0	0	0
T117	104079	330	0	0
T118	75738	0	0	0
T134	154559	0	0	0
T263	282811	0	0	0
T289	0	330	0	0
T290	0	330	0	0
T291	317969	0	0	0
T292	60941	0	0	0
T293	79783	0	0	0
T294	198721	0	0	0
T295	100229	0	0	0