Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.41	99.34	100.00			98.31	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	890	890	0	0
OutputsKnown_A	91661161	91121054	0	0
gen_no_flops.OutputDelay_A	91661161	91121054	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	890	890	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91661161	91121054	0	0
T1	41621	41154	0	0
T2	52065	51653	0	0
T3	27059	26299	0	0
T4	373411	370283	0	0
T5	53043	51050	0	0
T15	21246	20514	0	0
T30	160709	160294	0	0
T98	135475	135103	0	0
T112	15879	15543	0	0
T135	144774	143989	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91661161	91121054	0	0
T1	41621	41154	0	0
T2	52065	51653	0	0
T3	27059	26299	0	0
T4	373411	370283	0	0
T5	53043	51050	0	0
T15	21246	20514	0	0
T30	160709	160294	0	0
T98	135475	135103	0	0
T112	15879	15543	0	0
T135	144774	143989	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	890	890	0	0
OutputsKnown_A	91661161	91121054	0	0
gen_no_flops.OutputDelay_A	91661161	91121054	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	890	890	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T30	1	1	0	0
T98	1	1	0	0
T112	1	1	0	0
T135	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91661161	91121054	0	0
T1	41621	41154	0	0
T2	52065	51653	0	0
T3	27059	26299	0	0
T4	373411	370283	0	0
T5	53043	51050	0	0
T15	21246	20514	0	0
T30	160709	160294	0	0
T98	135475	135103	0	0
T112	15879	15543	0	0
T135	144774	143989	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91661161	91121054	0	0
T1	41621	41154	0	0
T2	52065	51653	0	0
T3	27059	26299	0	0
T4	373411	370283	0	0
T5	53043	51050	0	0
T15	21246	20514	0	0
T30	160709	160294	0	0
T98	135475	135103	0	0
T112	15879	15543	0	0
T135	144774	143989	0	0