Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3648927	1			T61	2087		T62	14		T63	7587
values[2]	740276	1			T61	586		T62	13		T63	1453
values[3]	109599	1			T61	9		T62	13		T63	24
values[4]	57323	1			T62	13		T230	138		T487	6
values[5]	37883	1			T62	14		T230	154		T487	6
values[6]	28513	1			T62	13		T230	109		T487	6
values[7]	22853	1			T62	13		T230	97		T487	6
values[8]	19267	1			T62	13		T230	88		T487	6
values[9]	17224	1			T62	14		T230	100		T487	6
values[10]	15855	1			T62	13		T230	146		T487	6
values[11]	14627	1			T62	14		T230	117		T487	6
values[12]	13697	1			T62	13		T230	97		T487	6
values[13]	13058	1			T62	13		T230	83		T487	6
values[14]	12570	1			T62	13		T230	73		T487	6
values[15]	12002	1			T62	13		T230	74		T487	6
values[16]	11270	1			T62	13		T230	65		T487	6
values[17]	10797	1			T62	13		T230	104		T487	6
values[18]	10587	1			T62	13		T230	110		T487	6
values[19]	9830	1			T62	13		T230	62		T487	6
values[20]	9673	1			T62	13		T230	87		T487	6
values[21]	9292	1			T62	13		T230	67		T487	6
values[22]	9097	1			T62	14		T230	54		T487	6
values[23]	8977	1			T62	13		T230	55		T487	6
values[24]	8847	1			T62	14		T230	85		T487	6
values[25]	8295	1			T62	13		T230	71		T487	6
values[26]	7800	1			T62	13		T230	58		T487	6
values[27]	7501	1			T62	13		T230	54		T487	6
values[28]	7166	1			T62	13		T230	39		T487	6
values[29]	6691	1			T62	14		T230	35		T487	7
values[30]	6026	1			T62	13		T230	35		T487	6
values[31]	5829	1			T62	14		T230	26		T487	6
values[32]	5597	1			T62	13		T230	35		T487	6
values[33]	5284	1			T62	13		T230	33		T487	6
values[34]	4892	1			T62	13		T230	31		T487	6
values[35]	4531	1			T62	13		T230	21		T487	7
values[36]	4378	1			T62	14		T230	19		T487	7
values[37]	3968	1			T62	14		T230	34		T487	6
values[38]	3814	1			T62	13		T230	30		T487	6
values[39]	3661	1			T62	13		T230	13		T487	6
values[40]	3665	1			T62	13		T230	11		T487	6
values[41]	3470	1			T62	13		T230	16		T487	6
values[42]	3351	1			T62	13		T230	9		T487	6
values[43]	3282	1			T62	13		T230	9		T487	6
values[44]	3063	1			T62	13		T230	7		T487	6
values[45]	3125	1			T62	13		T230	12		T487	6
values[46]	3006	1			T62	13		T230	15		T487	6
values[47]	2945	1			T62	13		T230	2		T487	6
values[48]	2941	1			T62	13		T230	2		T487	6
values[49]	2840	1			T62	14		T230	3		T487	6
values[50]	2741	1			T62	13		T230	4		T487	6
values[51]	2815	1			T62	14		T230	3		T487	6
values[52]	2715	1			T62	14		T230	3		T487	6
values[53]	2704	1			T62	13		T230	2		T487	6
values[54]	2510	1			T62	13		T230	4		T487	7
values[55]	2408	1			T62	13		T230	4		T487	6
values[56]	2469	1			T62	13		T230	3		T487	6
values[57]	2460	1			T62	13		T230	4		T487	7
values[58]	2453	1			T62	14		T230	9		T487	6
values[59]	2342	1			T62	13		T230	5		T487	6
values[60]	2400	1			T62	13		T230	4		T487	6
values[61]	2728	1			T62	14		T230	2		T487	6
values[62]	4377	1			T62	14		T230	3		T487	6
values[63]	15708	1			T62	14		T230	12		T487	8
values[64]	213904	1			T62	2501		T230	315		T487	1096

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4728627	1			T61	2444		T62	2206		T63	8144
values[2]	781721	1			T61	574		T62	605		T63	1171
values[3]	75785	1			T61	53		T62	172		T63	154
values[4]	13695	1			T61	4		T62	57		T63	5
values[5]	5725	1			T61	1		T62	20		T230	6
values[6]	3566	1			T62	6		T230	8		T487	4
values[7]	2799	1			T62	2		T230	10		T487	1
values[8]	2387	1			T62	1		T230	5		T487	1
values[9]	2137	1			T62	1		T230	4		T487	1
values[10]	1919	1			T62	1		T230	6		T487	1
values[11]	1798	1			T62	1		T230	10		T487	1
values[12]	1608	1			T62	1		T230	6		T487	1
values[13]	1553	1			T62	1		T230	5		T487	1
values[14]	1413	1			T62	1		T230	5		T487	1
values[15]	1302	1			T62	1		T230	5		T487	1
values[16]	1140	1			T62	1		T230	4		T487	1
values[17]	1146	1			T62	1		T230	4		T487	1
values[18]	1078	1			T62	1		T230	5		T487	1
values[19]	1098	1			T62	1		T230	6		T487	1
values[20]	1031	1			T62	1		T230	7		T487	1
values[21]	941	1			T62	1		T230	6		T487	1
values[22]	830	1			T62	1		T230	6		T487	1
values[23]	716	1			T62	1		T230	4		T487	1
values[24]	676	1			T62	1		T230	6		T487	1
values[25]	694	1			T62	1		T230	4		T487	1
values[26]	635	1			T62	1		T230	5		T487	1
values[27]	660	1			T62	1		T230	4		T487	1
values[28]	631	1			T62	1		T230	4		T487	1
values[29]	548	1			T62	1		T230	4		T487	1
values[30]	571	1			T62	1		T230	8		T487	1
values[31]	524	1			T62	1		T230	8		T487	1
values[32]	533	1			T62	1		T230	5		T487	1
values[33]	498	1			T62	1		T230	4		T487	1
values[34]	511	1			T62	1		T230	5		T487	1
values[35]	517	1			T62	1		T230	7		T487	1
values[36]	540	1			T62	1		T230	3		T487	1
values[37]	510	1			T62	1		T230	8		T487	1
values[38]	496	1			T62	1		T230	8		T487	1
values[39]	454	1			T62	1		T230	5		T487	1
values[40]	469	1			T62	1		T230	5		T487	1
values[41]	436	1			T62	1		T230	6		T487	1
values[42]	430	1			T62	1		T230	9		T487	1
values[43]	417	1			T62	1		T230	7		T487	1
values[44]	450	1			T62	1		T230	4		T487	1
values[45]	418	1			T62	1		T230	4		T487	1
values[46]	427	1			T62	1		T230	5		T487	1
values[47]	439	1			T62	1		T230	7		T487	1
values[48]	439	1			T62	1		T230	5		T487	1
values[49]	395	1			T62	1		T230	5		T487	1
values[50]	362	1			T62	1		T230	4		T487	1
values[51]	388	1			T62	1		T230	5		T487	1
values[52]	386	1			T62	1		T230	9		T487	1
values[53]	389	1			T62	1		T230	4		T487	1
values[54]	449	1			T62	1		T230	8		T487	1
values[55]	415	1			T62	1		T230	8		T487	1
values[56]	419	1			T62	1		T230	12		T487	1
values[57]	383	1			T62	1		T230	8		T487	1
values[58]	362	1			T62	1		T230	5		T487	1
values[59]	368	1			T62	1		T230	5		T487	1
values[60]	351	1			T62	1		T230	6		T487	1
values[61]	407	1			T62	1		T230	9		T487	1
values[62]	648	1			T62	1		T230	5		T487	1
values[63]	3440	1			T62	1		T230	24		T487	2
values[64]	24138	1			T62	157		T230	385		T487	156

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	595763	1			T61	20		T62	13		T63	1781
values[2]	2599900	1			T61	929		T62	13		T63	5559
values[3]	1136645	1			T61	1710		T62	14		T63	1131
values[4]	153600	1			T61	35		T62	13		T63	107
values[5]	77786	1			T62	13		T63	86		T230	237
values[6]	50778	1			T62	13		T63	54		T230	182
values[7]	36738	1			T62	13		T63	24		T230	121
values[8]	28933	1			T62	13		T63	20		T230	103
values[9]	24602	1			T62	13		T63	37		T230	99
values[10]	21678	1			T62	13		T63	16		T230	144
values[11]	19114	1			T62	13		T63	18		T230	123
values[12]	18111	1			T62	13		T63	25		T230	86
values[13]	16639	1			T62	13		T63	35		T230	87
values[14]	15786	1			T62	13		T63	21		T230	82
values[15]	14614	1			T62	13		T63	5		T230	91
values[16]	13929	1			T62	13		T230	125		T487	6
values[17]	13144	1			T62	13		T230	120		T487	6
values[18]	12455	1			T62	13		T230	91		T487	6
values[19]	11900	1			T62	13		T230	88		T487	6
values[20]	11448	1			T62	13		T230	83		T487	8
values[21]	11074	1			T62	13		T230	75		T487	6
values[22]	10659	1			T62	13		T230	80		T487	6
values[23]	10039	1			T62	13		T230	80		T487	7
values[24]	9619	1			T62	13		T230	59		T487	6
values[25]	9343	1			T62	13		T230	61		T487	6
values[26]	9038	1			T62	13		T230	92		T487	6
values[27]	8790	1			T62	13		T230	82		T487	6
values[28]	8382	1			T62	13		T230	52		T487	6
values[29]	7818	1			T62	13		T230	81		T487	6
values[30]	7193	1			T62	13		T230	49		T487	6
values[31]	6798	1			T62	13		T230	87		T487	6
values[32]	6112	1			T62	13		T230	76		T487	6
values[33]	5808	1			T62	13		T230	39		T487	6
values[34]	5430	1			T62	14		T230	24		T487	6
values[35]	5141	1			T62	13		T230	20		T487	6
values[36]	4908	1			T62	13		T230	23		T487	6
values[37]	4535	1			T62	13		T230	18		T487	6
values[38]	4202	1			T62	13		T230	11		T487	6
values[39]	4139	1			T62	13		T230	19		T487	6
values[40]	3907	1			T62	13		T230	12		T487	6
values[41]	3717	1			T62	14		T230	17		T487	6
values[42]	3693	1			T62	13		T230	8		T487	6
values[43]	3621	1			T62	14		T230	15		T487	6
values[44]	3530	1			T62	13		T230	15		T487	6
values[45]	3481	1			T62	13		T230	15		T487	6
values[46]	3542	1			T62	13		T230	17		T487	6
values[47]	3381	1			T62	13		T230	23		T487	7
values[48]	3258	1			T62	13		T230	16		T487	7
values[49]	3224	1			T62	13		T230	18		T487	6
values[50]	3289	1			T62	14		T230	11		T487	7
values[51]	3220	1			T62	14		T230	6		T487	6
values[52]	3111	1			T62	13		T230	19		T487	6
values[53]	2994	1			T62	13		T230	15		T487	6
values[54]	2928	1			T62	13		T230	17		T487	6
values[55]	2929	1			T62	13		T230	12		T487	6
values[56]	2857	1			T62	13		T230	3		T487	6
values[57]	2807	1			T62	13		T230	3		T487	6
values[58]	2699	1			T62	13		T230	3		T487	6
values[59]	2580	1			T62	13		T230	5		T487	6
values[60]	2607	1			T62	13		T230	3		T487	6
values[61]	2919	1			T62	13		T230	3		T487	6
values[62]	4037	1			T62	14		T230	2		T487	6
values[63]	19591	1			T62	14		T230	3		T487	6
values[64]	200256	1			T62	2382		T230	327		T487	1105