Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1859442	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27789163

1

T1

14760

T2

4496

T3

20915

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	20435579	1			T1	6456		T2	1518		T3	16403
values[0x0]	7752427	1			T1	8304		T2	2978		T3	4512
values[0x1]	1460599	1			T1	1106		T2	151		T3	4431

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	553979	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29094626

1

T1

15866

T2

4647

T3

25346

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13752186	1			T1	7934		T2	2324		T3	12673
valid_sources[0x01]	13750902	1			T1	7932		T2	2323		T3	12673
valid_sources[0x02]	37280	1			T425	1		T232	3		T364	8
valid_sources[0x03]	34096	1			T46	1		T425	2		T232	2
valid_sources[0x04]	34558	1			T364	14		T178	100		T838	219
valid_sources[0x05]	34219	1			T46	1		T65	2		T364	11
valid_sources[0x06]	34922	1			T425	1		T232	1		T364	11
valid_sources[0x07]	34568	1			T425	2		T364	14		T178	71
valid_sources[0x08]	34242	1			T46	1		T364	12		T178	100
valid_sources[0x09]	34441	1			T46	1		T232	1		T364	13
valid_sources[0x0a]	34112	1			T232	1		T364	11		T178	111
valid_sources[0x0b]	34825	1			T66	39		T364	14		T178	68
valid_sources[0x0c]	34598	1			T232	1		T364	7		T178	98
valid_sources[0x0d]	33841	1			T65	2		T232	2		T364	8
valid_sources[0x0e]	38001	1			T46	1		T364	13		T178	127
valid_sources[0x0f]	34856	1			T46	2		T232	1		T364	13
valid_sources[0x10]	34341	1			T46	1		T65	10		T364	17
valid_sources[0x11]	34197	1			T46	1		T232	1		T364	11
valid_sources[0x12]	34831	1			T46	1		T364	11		T178	67
valid_sources[0x13]	35074	1			T364	10		T178	77		T838	257
valid_sources[0x14]	34929	1			T65	6		T232	1		T364	11
valid_sources[0x15]	34596	1			T65	4		T231	39		T364	17
valid_sources[0x16]	34161	1			T46	3		T232	2		T364	10
valid_sources[0x17]	34915	1			T46	1		T425	4		T364	7
valid_sources[0x18]	34969	1			T364	13		T178	63		T838	242
valid_sources[0x19]	34237	1			T46	1		T425	1		T232	1
valid_sources[0x1a]	34241	1			T46	1		T425	6		T232	1
valid_sources[0x1b]	34364	1			T46	1		T425	1		T232	2
valid_sources[0x1c]	33868	1			T232	1		T364	12		T178	80
valid_sources[0x1d]	34274	1			T65	2		T364	9		T178	70
valid_sources[0x1e]	33584	1			T232	3		T364	12		T178	70
valid_sources[0x1f]	34672	1			T232	1		T364	6		T178	59
valid_sources[0x20]	35172	1			T46	1		T425	3		T232	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19828474

1

T1

6456

T2

1518

T3

16403

values[0x0]

all_enables

biggest_size

7711671

1

T1

8304

T2

2978

T3

4512

values[0x1]

all_enables

biggest_size

249018

1

T46

19

T65

27

T66

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2848814	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

450428

1

T61

6

T62

444

T63

1202

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1117004	1			T61	54		T62	1110		T63	3057
values[0x0]	1065191	1			T61	5		T62	1132		T63	2919
values[0x1]	1117047	1			T61	60		T62	1095		T63	3088

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2206859	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1092383

1

T61

49

T62

1051

T63

2958

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51903	1			T61	3		T62	55		T63	126
valid_sources[0x01]	52305	1			T61	2		T62	44		T63	146
valid_sources[0x02]	51861	1			T62	40		T63	118		T67	84
valid_sources[0x03]	52042	1			T61	1		T62	50		T63	149
valid_sources[0x04]	50658	1			T61	4		T62	59		T63	166
valid_sources[0x05]	51741	1			T61	1		T62	49		T63	135
valid_sources[0x06]	51598	1			T61	2		T62	48		T63	155
valid_sources[0x07]	51154	1			T62	53		T63	125		T67	38
valid_sources[0x08]	52010	1			T61	3		T62	62		T63	168
valid_sources[0x09]	50649	1			T61	3		T62	57		T63	122
valid_sources[0x0a]	51802	1			T61	4		T62	55		T63	158
valid_sources[0x0b]	50615	1			T61	1		T62	65		T63	152
valid_sources[0x0c]	51519	1			T61	1		T62	40		T63	163
valid_sources[0x0d]	52812	1			T61	1		T62	52		T63	173
valid_sources[0x0e]	51647	1			T61	3		T62	49		T63	164
valid_sources[0x0f]	51074	1			T61	1		T62	49		T63	135
valid_sources[0x10]	52268	1			T61	1		T62	64		T63	132
valid_sources[0x11]	51378	1			T61	4		T62	63		T63	127
valid_sources[0x12]	51763	1			T61	2		T62	46		T63	123
valid_sources[0x13]	52367	1			T61	1		T62	53		T63	151
valid_sources[0x14]	51647	1			T61	4		T62	44		T63	126
valid_sources[0x15]	50901	1			T62	57		T63	138		T67	39
valid_sources[0x16]	51725	1			T62	52		T63	107		T67	8
valid_sources[0x17]	51788	1			T61	1		T62	51		T63	132
valid_sources[0x18]	51543	1			T61	3		T62	41		T63	141
valid_sources[0x19]	51745	1			T62	53		T63	140		T67	45
valid_sources[0x1a]	52438	1			T61	2		T62	57		T63	91
valid_sources[0x1b]	51497	1			T61	1		T62	61		T63	167
valid_sources[0x1c]	50892	1			T61	2		T62	55		T63	150
valid_sources[0x1d]	51682	1			T61	3		T62	46		T63	150
valid_sources[0x1e]	52325	1			T61	1		T62	54		T63	132
valid_sources[0x1f]	51858	1			T62	45		T63	163		T67	22
valid_sources[0x20]	50895	1			T61	3		T62	45		T63	131

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47142

1

T61

2

T62

46

T63

122

values[0x0]

all_enables

biggest_size

355972

1

T61

2

T62

358

T63

962

values[0x1]

all_enables

biggest_size

47314

1

T61

2

T62

40

T63

118

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3054753	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

498577

1

T61

18

T62

463

T63

1348

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1215907	1			T61	70		T62	1124		T63	3237
values[0x0]	1121560	1			T61	13		T62	1007		T63	3058
values[0x1]	1215863	1			T61	62		T62	1150		T63	3179

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2344754	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1208576

1

T61

67

T62

1103

T63

3201

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55848	1			T61	4		T62	44		T63	145
valid_sources[0x01]	55322	1			T61	1		T62	39		T63	124
valid_sources[0x02]	55769	1			T61	1		T62	44		T63	100
valid_sources[0x03]	55343	1			T61	3		T62	69		T63	129
valid_sources[0x04]	54832	1			T61	3		T62	59		T63	157
valid_sources[0x05]	54968	1			T61	4		T62	51		T63	121
valid_sources[0x06]	55096	1			T61	7		T62	53		T63	167
valid_sources[0x07]	55590	1			T61	4		T62	51		T63	122
valid_sources[0x08]	56147	1			T61	3		T62	68		T63	176
valid_sources[0x09]	54616	1			T61	1		T62	51		T63	134
valid_sources[0x0a]	55905	1			T61	8		T62	43		T63	184
valid_sources[0x0b]	55512	1			T61	2		T62	54		T63	152
valid_sources[0x0c]	56129	1			T62	56		T63	184		T67	31
valid_sources[0x0d]	55724	1			T62	51		T63	181		T67	23
valid_sources[0x0e]	55453	1			T62	59		T63	165		T491	1
valid_sources[0x0f]	55309	1			T62	51		T63	155		T67	17
valid_sources[0x10]	55642	1			T62	52		T63	133		T67	21
valid_sources[0x11]	54926	1			T61	4		T62	51		T63	142
valid_sources[0x12]	55958	1			T62	54		T63	127		T67	39
valid_sources[0x13]	55554	1			T61	4		T62	49		T63	160
valid_sources[0x14]	54774	1			T62	53		T63	134		T67	73
valid_sources[0x15]	54069	1			T61	1		T62	53		T63	179
valid_sources[0x16]	56244	1			T62	54		T63	124		T67	15
valid_sources[0x17]	56108	1			T61	1		T62	57		T63	144
valid_sources[0x18]	56172	1			T61	3		T62	52		T63	110
valid_sources[0x19]	55697	1			T62	36		T63	148		T67	53
valid_sources[0x1a]	55000	1			T61	1		T62	46		T63	123
valid_sources[0x1b]	54844	1			T61	4		T62	43		T63	170
valid_sources[0x1c]	55699	1			T61	6		T62	55		T63	184
valid_sources[0x1d]	54913	1			T61	2		T62	43		T63	114
valid_sources[0x1e]	55860	1			T61	3		T62	59		T63	151
valid_sources[0x1f]	55828	1			T61	4		T62	48		T63	192
valid_sources[0x20]	54683	1			T61	5		T62	41		T63	164

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52433

1

T61

6

T62

52

T63

152

values[0x0]

all_enables

biggest_size

394235

1

T61

8

T62

357

T63

1061

values[0x1]

all_enables

biggest_size

51909

1

T61

4

T62

54

T63

135

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2890046	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

456285

1

T61

12

T62

420

T63

1238

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1132658	1			T61	62		T62	1078		T63	2939
values[0x0]	1080018	1			T61	5		T62	1043		T63	2858
values[0x1]	1133655	1			T61	70		T62	1088		T63	3122

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2236823	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1109508

1

T61

50

T62

1073

T63

2954

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52827	1			T61	1		T62	52		T63	94
valid_sources[0x01]	52069	1			T61	7		T62	43		T63	127
valid_sources[0x02]	52089	1			T62	51		T63	136		T67	90
valid_sources[0x03]	52577	1			T61	4		T62	43		T63	159
valid_sources[0x04]	52389	1			T61	3		T62	50		T63	148
valid_sources[0x05]	52704	1			T61	2		T62	60		T63	118
valid_sources[0x06]	52307	1			T62	43		T63	179		T67	44
valid_sources[0x07]	52221	1			T61	5		T62	54		T63	109
valid_sources[0x08]	52876	1			T61	5		T62	37		T63	180
valid_sources[0x09]	51795	1			T61	3		T62	45		T63	163
valid_sources[0x0a]	52272	1			T61	3		T62	36		T63	186
valid_sources[0x0b]	52444	1			T61	3		T62	52		T63	141
valid_sources[0x0c]	52779	1			T62	47		T63	181		T67	56
valid_sources[0x0d]	52831	1			T62	63		T63	164		T67	30
valid_sources[0x0e]	52604	1			T61	2		T62	54		T63	155
valid_sources[0x0f]	52501	1			T61	2		T62	49		T63	132
valid_sources[0x10]	52138	1			T62	53		T63	127		T67	25
valid_sources[0x11]	52839	1			T61	1		T62	46		T63	111
valid_sources[0x12]	51249	1			T61	1		T62	45		T63	132
valid_sources[0x13]	52166	1			T61	1		T62	48		T63	127
valid_sources[0x14]	52000	1			T61	4		T62	47		T63	105
valid_sources[0x15]	51479	1			T61	2		T62	39		T63	156
valid_sources[0x16]	53267	1			T61	1		T62	50		T63	127
valid_sources[0x17]	52151	1			T61	2		T62	49		T63	136
valid_sources[0x18]	52536	1			T61	2		T62	56		T63	97
valid_sources[0x19]	53021	1			T61	3		T62	51		T63	184
valid_sources[0x1a]	51943	1			T61	4		T62	53		T63	118
valid_sources[0x1b]	52044	1			T61	3		T62	50		T63	149
valid_sources[0x1c]	52212	1			T61	2		T62	59		T63	171
valid_sources[0x1d]	51808	1			T61	1		T62	50		T63	145
valid_sources[0x1e]	52703	1			T61	1		T62	47		T63	130
valid_sources[0x1f]	51855	1			T61	2		T62	51		T63	182
valid_sources[0x20]	51673	1			T62	48		T63	145		T67	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47746

1

T61

5

T62

43

T63

121

values[0x0]

all_enables

biggest_size

360618

1

T61

3

T62

336

T63

995

values[0x1]

all_enables

biggest_size

47921

1

T61

4

T62

41

T63

122