Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_dm 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_dm

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.09 90.68 88.59 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : rv_dm
TotalCoveredPercent
Totals 86 86 100.00
Total Bits 938 938 100.00
Total Bits 0->1 469 469 100.00
Total Bits 1->0 469 469 100.00

Ports 86 86 100.00
Port Bits 938 938 100.00
Port Bits 0->1 469 469 100.00
Port Bits 1->0 469 469 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_lc_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T31,T32 Yes T1,T2,T3 INPUT
rst_lc_ni Yes Yes T1,T31,T32 Yes T1,T2,T3 INPUT
next_dm_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
lc_hw_debug_en_i[3:0] Yes Yes T1,T31,T32 Yes T1,T2,T3 INPUT
lc_dft_en_i[3:0] Yes Yes T1,T31,T32 Yes T1,T2,T3 INPUT
pinmux_hw_debug_en_i[3:0] Yes Yes T1,T31,T32 Yes T1,T2,T3 INPUT
otp_dis_rv_dm_late_debug_i[7:0] Yes Yes T1,T2,T3 Yes T1,T31,T32 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
ndmreset_req_o Yes Yes T108,T53,T64 Yes T108,T53,T64 OUTPUT
dmactive_o Yes Yes T46,T185,T65 Yes T46,T108,T47 OUTPUT
debug_req_o Yes Yes T64,T71,T72 Yes T64,T71,T72 OUTPUT
unavailable_i Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.d_ready Yes Yes T1,T31,T32 Yes T1,T2,T3 INPUT
regs_tl_d_i.a_user.data_intg[6:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 INPUT
regs_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 INPUT
regs_tl_d_i.a_user.instr_type[3:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 INPUT
regs_tl_d_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_data[31:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 INPUT
regs_tl_d_i.a_mask[3:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 INPUT
regs_tl_d_i.a_address[3:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 INPUT
regs_tl_d_i.a_address[20:4] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_address[21] Yes Yes *T61,*T63,*T67 Yes T61,T63,T67 INPUT
regs_tl_d_i.a_address[23:22] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_address[24] Yes Yes *T61,*T63,*T67 Yes T61,T63,T67 INPUT
regs_tl_d_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_address[30] Yes Yes *T61,*T63,*T67 Yes T61,T63,T67 INPUT
regs_tl_d_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_source[5:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 INPUT
regs_tl_d_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_size[1:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 INPUT
regs_tl_d_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_d_i.a_opcode[2:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 INPUT
regs_tl_d_i.a_valid Yes Yes T61,T63,T67 Yes T61,T63,T67 INPUT
regs_tl_d_o.a_ready Yes Yes T61,T62,T63 Yes T61,T62,T63 OUTPUT
regs_tl_d_o.d_error Yes Yes T61,T63,T67 Yes T61,T63,T67 OUTPUT
regs_tl_d_o.d_user.data_intg[6:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 OUTPUT
regs_tl_d_o.d_user.rsp_intg[6:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 OUTPUT
regs_tl_d_o.d_data[31:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 OUTPUT
regs_tl_d_o.d_sink Yes Yes T61,T63,T67 Yes T61,T63,T67 OUTPUT
regs_tl_d_o.d_source[5:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 OUTPUT
regs_tl_d_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_d_o.d_size[1:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 OUTPUT
regs_tl_d_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_d_o.d_opcode[0] Yes Yes *T61,*T63,*T67 Yes T61,T63,T67 OUTPUT
regs_tl_d_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_d_o.d_valid Yes Yes T61,T63,T67 Yes T61,T63,T67 OUTPUT
mem_tl_d_i.d_ready Yes Yes T1,T31,T32 Yes T1,T2,T3 INPUT
mem_tl_d_i.a_user.data_intg[6:0] Yes Yes T64,T71,T72 Yes T64,T71,T72 INPUT
mem_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T64,T71,T72 Yes T64,T71,T72 INPUT
mem_tl_d_i.a_user.instr_type[3:0] Yes Yes T64,T71,T72 Yes T64,T71,T72 INPUT
mem_tl_d_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
mem_tl_d_i.a_data[31:0] Yes Yes T64,T71,T72 Yes T64,T71,T72 INPUT
mem_tl_d_i.a_mask[3:0] Yes Yes T64,T71,T72 Yes T64,T71,T72 INPUT
mem_tl_d_i.a_address[11:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
mem_tl_d_i.a_address[15:12] Unreachable Unreachable Unreachable INPUT
mem_tl_d_i.a_address[16] Yes Yes *T64,*T71,*T72 Yes T64,T71,T72 INPUT
mem_tl_d_i.a_address[31:17] Unreachable Unreachable Unreachable INPUT
mem_tl_d_i.a_source[5:0] Yes Yes *T64,*T71,*T72 Yes T64,T71,T72 INPUT
mem_tl_d_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
mem_tl_d_i.a_size[1:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
mem_tl_d_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
mem_tl_d_i.a_opcode[2:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
mem_tl_d_i.a_valid Yes Yes T64,T71,T72 Yes T64,T71,T72 INPUT
mem_tl_d_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_d_o.d_error Yes Yes T1,T2,T3 Yes T1,T31,T32 OUTPUT
mem_tl_d_o.d_user.data_intg[6:0] Yes Yes T64,T71,T72 Yes T64,T71,T72 OUTPUT
mem_tl_d_o.d_user.rsp_intg[6:0] Yes Yes T64,T71,T72 Yes T64,T71,T72 OUTPUT
mem_tl_d_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T31,T32 OUTPUT
mem_tl_d_o.d_sink Yes Yes T61,T62,T63 Yes T61,T62,T63 OUTPUT
mem_tl_d_o.d_source[5:0] Yes Yes *T64,*T71,*T72 Yes T64,T71,T72 OUTPUT
mem_tl_d_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
mem_tl_d_o.d_size[1:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 OUTPUT
mem_tl_d_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
mem_tl_d_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T31,T32 OUTPUT
mem_tl_d_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
mem_tl_d_o.d_valid Yes Yes T64,T71,T72 Yes T64,T71,T72 OUTPUT
sba_tl_h_o.d_ready Yes Yes T1,T31,T32 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.data_intg[6:0] Yes Yes T46,T47,T73 Yes T46,T47,T73 OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T1,T31,T32 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[3:0] Yes Yes T1,T31,T32 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
sba_tl_h_o.a_data[31:0] Yes Yes T46,T47,T73 Yes T46,T47,T73 OUTPUT
sba_tl_h_o.a_mask[3:0] Yes Yes T1,T31,T32 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_address[31:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 OUTPUT
sba_tl_h_o.a_source[5:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 OUTPUT
sba_tl_h_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
sba_tl_h_o.a_size[1:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 OUTPUT
sba_tl_h_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
sba_tl_h_o.a_opcode[2:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 OUTPUT
sba_tl_h_o.a_valid Yes Yes T46,T47,T73 Yes T46,T47,T73 OUTPUT
sba_tl_h_i.a_ready Yes Yes T1,T31,T32 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_error Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
sba_tl_h_i.d_user.data_intg[6:0] Yes Yes T46,T47,T73 Yes T46,T47,T73 INPUT
sba_tl_h_i.d_user.rsp_intg[6:0] Yes Yes T46,T47,T73 Yes T46,T47,T73 INPUT
sba_tl_h_i.d_data[31:0] Yes Yes T46,T47,T73 Yes T46,T47,T73 INPUT
sba_tl_h_i.d_sink Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
sba_tl_h_i.d_source[5:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
sba_tl_h_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
sba_tl_h_i.d_size[1:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
sba_tl_h_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
sba_tl_h_i.d_opcode[0] Yes Yes *T46,*T47,*T73 Yes T46,T47,T73 INPUT
sba_tl_h_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
sba_tl_h_i.d_valid Yes Yes T46,T47,T73 Yes T46,T47,T73 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T75,T665,T83 Yes T75,T665,T83 INPUT
alert_rx_i[0].ping_n Yes Yes T75,T83,T77 Yes T75,T83,T77 INPUT
alert_rx_i[0].ping_p Yes Yes T75,T83,T77 Yes T75,T83,T77 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T75,T665,T83 Yes T75,T665,T83 OUTPUT
jtag_i.tdi Yes Yes T46,T108,T47 Yes T46,T108,T47 INPUT
jtag_i.trst_n Yes Yes T46,T47,T73 Yes T46,T108,T47 INPUT
jtag_i.tms Yes Yes T46,T108,T47 Yes T46,T108,T47 INPUT
jtag_i.tck Yes Yes T46,T108,T47 Yes T46,T108,T47 INPUT
jtag_o.tdo_oe Yes Yes T46,T108,T47 Yes T46,T108,T47 OUTPUT
jtag_o.tdo Yes Yes T46,T108,T47 Yes T46,T108,T47 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%