Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : csrng
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.27 99.27

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_csrng_0.1/rtl/csrng.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_csrng 99.27 99.27



Module Instance : tb.dut.top_earlgrey.u_csrng

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.27 99.27


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.27 99.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.09 90.68 88.59 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : csrng
TotalCoveredPercent
Totals 65 62 95.38
Total Bits 1790 1777 99.27
Total Bits 0->1 895 889 99.33
Total Bits 1->0 895 888 99.22

Ports 65 62 95.38
Port Bits 1790 1777 99.27
Port Bits 0->1 895 889 99.33
Port Bits 1->0 895 888 99.22

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T31,T32 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T95,T91,T132 Yes T95,T91,T132 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T61,*T63,*T67 Yes T61,T63,T67 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T46,*T65,*T231 Yes T46,T65,T231 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T61,T63,T67 Yes T61,T63,T67 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T95,T91,T132 Yes T95,T91,T132 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T95,T31 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T31,T32 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T61,T63,T67 Yes T61,T63,T67 OUTPUT
tl_o.d_source[5:0] Yes Yes *T46,*T65,*T231 Yes T46,T65,T231 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T61,T63,T67 Yes T61,T63,T67 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T95,*T91,*T132 Yes T95,T91,T132 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_en_csrng_sw_app_read_i[7:0] Yes Yes T1,T2,T3 Yes T1,T31,T32 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T1,T31,T32 Yes T1,T2,T3 INPUT
entropy_src_hw_if_o.es_req Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
entropy_src_hw_if_i.es_fips Yes Yes T68,T69,T70 Yes T95,T91,T132 INPUT
entropy_src_hw_if_i.es_bits[383:0] Yes Yes T95,T91,T132 Yes T95,T91,T132 INPUT
entropy_src_hw_if_i.es_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cs_aes_halt_i.cs_aes_halt_req Yes Yes T95,T91,T132 Yes T95,T91,T132 INPUT
cs_aes_halt_o.cs_aes_halt_ack Yes Yes T95,T91,T132 Yes T95,T91,T132 OUTPUT
csrng_cmd_i[0].genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i[0].csrng_req_bus[31:0] Yes Yes T1,T95,T31 Yes T1,T2,T3 INPUT
csrng_cmd_i[0].csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i[1].genbits_ready Yes Yes T95,T91,T132 Yes T95,T91,T132 INPUT
csrng_cmd_i[1].csrng_req_bus[31:0] Yes Yes T95,T91,T132 Yes T95,T91,T132 INPUT
csrng_cmd_i[1].csrng_req_valid Yes Yes T95,T91,T132 Yes T95,T91,T132 INPUT
csrng_cmd_o[0].genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o[0].genbits_fips Yes Yes T149,T644,T172 Yes T95,T91,T98 OUTPUT
csrng_cmd_o[0].genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o[0].csrng_rsp_sts[2:0] No No No OUTPUT
csrng_cmd_o[0].csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o[0].csrng_req_ready Yes Yes T132,T252,T157 Yes T132,T252,T157 OUTPUT
csrng_cmd_o[1].genbits_bus[127:0] Yes Yes T95,T91,T132 Yes T95,T91,T98 OUTPUT
csrng_cmd_o[1].genbits_fips No No Yes T644,T647,T648 OUTPUT
csrng_cmd_o[1].genbits_valid Yes Yes T95,T91,T132 Yes T95,T91,T132 OUTPUT
csrng_cmd_o[1].csrng_rsp_sts[2:0] No No No OUTPUT
csrng_cmd_o[1].csrng_rsp_ack Yes Yes T95,T91,T132 Yes T95,T91,T132 OUTPUT
csrng_cmd_o[1].csrng_req_ready Yes Yes T157,T240,T241 Yes T157,T240,T241 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T75,T252,T46 Yes T75,T252,T46 INPUT
alert_rx_i[0].ping_n Yes Yes T75,T83,T77 Yes T75,T83,T77 INPUT
alert_rx_i[0].ping_p Yes Yes T75,T83,T77 Yes T75,T83,T77 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T75,T46,T83 Yes T75,T46,T83 INPUT
alert_rx_i[1].ping_n Yes Yes T75,T83,T77 Yes T75,T83,T77 INPUT
alert_rx_i[1].ping_p Yes Yes T75,T83,T77 Yes T75,T83,T77 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T75,T252,T46 Yes T75,T252,T46 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T75,T46,T83 Yes T75,T46,T83 OUTPUT
intr_cs_cmd_req_done_o Yes Yes T283,T312,T323 Yes T283,T312,T323 OUTPUT
intr_cs_entropy_req_o Yes Yes T263,T283,T320 Yes T263,T283,T320 OUTPUT
intr_cs_hw_inst_exc_o Yes Yes T283,T312,T323 Yes T283,T312,T323 OUTPUT
intr_cs_fatal_err_o Yes Yes T283,T312,T323 Yes T283,T312,T323 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%