Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	381640490	43529029	0	0
DepthKnown_A	381640490	381551134	0	0
RvalidKnown_A	381640490	381551134	0	0
WreadyKnown_A	381640490	381551134	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	43529029	0	0
T1	245019	30930	0	0
T2	76918	9258	0	0
T3	241846	25308	0	0
T4	115290	126527	0	0
T31	520954	45846	0	0
T32	289301	36036	0	0
T44	124916	137601	0	0
T92	148219	18319	0	0
T95	143581	43582	0	0
T115	80803	8493	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	381551134	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	381551134	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	381551134	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	381640490	34855003	0	0
DepthKnown_A	381640490	381551134	0	0
RvalidKnown_A	381640490	381551134	0	0
WreadyKnown_A	381640490	381551134	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	34855003	0	0
T1	245019	21728	0	0
T2	76918	6446	0	0
T3	241846	21416	0	0
T4	115290	109277	0	0
T31	520954	32480	0	0
T32	289301	27247	0	0
T44	124916	119111	0	0
T92	148219	15906	0	0
T95	143581	39565	0	0
T115	80803	6329	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	381551134	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	381551134	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	381551134	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	381640490	33149521	0	0
DepthKnown_A	381640490	381551134	0	0
RvalidKnown_A	381640490	381551134	0	0
WreadyKnown_A	381640490	381551134	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	33149521	0	0
T1	245019	16256	0	0
T2	76918	4906	0	0
T3	241846	25549	0	0
T4	115290	185375	0	0
T31	520954	19554	0	0
T32	289301	20450	0	0
T44	124916	192200	0	0
T92	148219	5736	0	0
T95	143581	33089	0	0
T115	80803	4192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	381551134	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	381551134	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	381551134	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	381640490	27521333	0	0
DepthKnown_A	381640490	381551134	0	0
RvalidKnown_A	381640490	381551134	0	0
WreadyKnown_A	381640490	381551134	0	0
gen_passthru_fifo.paramCheckPass	905	905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	27521333	0	0
T1	245019	15866	0	0
T2	76918	4647	0	0
T3	241846	25346	0	0
T4	115290	101882	0	0
T31	520954	18796	0	0
T32	289301	20090	0	0
T44	124916	111200	0	0
T92	148219	5567	0	0
T95	143581	32918	0	0
T115	80803	4050	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	381551134	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	381551134	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	381551134	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460578286	79167	0	0
DepthKnown_A	460578286	460477223	0	0
RvalidKnown_A	460578286	460477223	0	0
WreadyKnown_A	460578286	460477223	0	0
gen_passthru_fifo.paramCheckPass	2795	2795	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	79167	0	0
T1	245019	151	0	0
T2	76918	27	0	0
T3	241846	53	0	0
T4	115290	27	0	0
T31	520954	181	0	0
T32	289301	151	0	0
T44	124916	34	0	0
T92	148219	47	0	0
T95	143581	29	0	0
T115	80803	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2795	2795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460578286	81278	0	0
DepthKnown_A	460578286	460477223	0	0
RvalidKnown_A	460578286	460477223	0	0
WreadyKnown_A	460578286	460477223	0	0
gen_passthru_fifo.paramCheckPass	2795	2795	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	81278	0	0
T1	245019	151	0	0
T2	76918	27	0	0
T3	241846	53	0	0
T4	115290	27	0	0
T31	520954	181	0	0
T32	289301	151	0	0
T44	124916	34	0	0
T92	148219	47	0	0
T95	143581	29	0	0
T115	80803	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2795	2795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460578286	46835	0	0
DepthKnown_A	460578286	460477223	0	0
RvalidKnown_A	460578286	460477223	0	0
WreadyKnown_A	460578286	460477223	0	0
gen_passthru_fifo.paramCheckPass	2795	2795	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	46835	0	0
T1	245019	95	0	0
T2	76918	24	0	0
T3	241846	52	0	0
T4	115290	0	0	0
T31	520954	176	0	0
T32	289301	95	0	0
T44	124916	5	0	0
T92	148219	46	0	0
T95	143581	28	0	0
T103	0	23	0	0
T115	80803	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2795	2795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460578286	46835	0	0
DepthKnown_A	460578286	460477223	0	0
RvalidKnown_A	460578286	460477223	0	0
WreadyKnown_A	460578286	460477223	0	0
gen_passthru_fifo.paramCheckPass	2795	2795	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	46835	0	0
T1	245019	95	0	0
T2	76918	24	0	0
T3	241846	52	0	0
T4	115290	0	0	0
T31	520954	176	0	0
T32	289301	95	0	0
T44	124916	5	0	0
T92	148219	46	0	0
T95	143581	28	0	0
T103	0	23	0	0
T115	80803	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2795	2795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460578286	32332	0	0
DepthKnown_A	460578286	460477223	0	0
RvalidKnown_A	460578286	460477223	0	0
WreadyKnown_A	460578286	460477223	0	0
gen_passthru_fifo.paramCheckPass	2795	2795	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	32332	0	0
T1	245019	56	0	0
T2	76918	3	0	0
T3	241846	1	0	0
T4	115290	27	0	0
T31	520954	5	0	0
T32	289301	56	0	0
T44	124916	29	0	0
T92	148219	1	0	0
T95	143581	1	0	0
T115	80803	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2795	2795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460578286	34443	0	0
DepthKnown_A	460578286	460477223	0	0
RvalidKnown_A	460578286	460477223	0	0
WreadyKnown_A	460578286	460477223	0	0
gen_passthru_fifo.paramCheckPass	2795	2795	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	34443	0	0
T1	245019	56	0	0
T2	76918	3	0	0
T3	241846	1	0	0
T4	115290	27	0	0
T31	520954	5	0	0
T32	289301	56	0	0
T44	124916	29	0	0
T92	148219	1	0	0
T95	143581	1	0	0
T115	80803	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460578286	460477223	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2795	2795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0