Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_3.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T178,T179,T180 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T179,T180,T355 |
1 | 0 | Covered | T179,T180,T355 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T178,T179,T180 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_4.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_4.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T403,T406,T178 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T179,T180,T355 |
1 | 0 | Covered | T403,T179,T180 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T403,T406,T178 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_5.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_5.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T403,T178,T420 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T179,T180,T354 |
1 | 0 | Covered | T420,T393,T476 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T403,T178,T420 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_6.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_6.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T486,T178,T430 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T178,T179,T180 |
1 | 0 | Covered | T486,T178,T430 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T486,T178,T430 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_7.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_7.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T406,T178,T404 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T178,T179,T352 |
1 | 0 | Covered | T406,T178,T179 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T406,T178,T404 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_8.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_8.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T406,T178,T423 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T178,T179,T354 |
1 | 0 | Covered | T178,T179,T470 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T406,T178,T423 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_9.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_9.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T406,T432,T178 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T179,T180,T355 |
1 | 0 | Covered | T432,T179,T180 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T406,T432,T178 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_10.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_10.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T432,T178,T430 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T179,T355,T354 |
1 | 0 | Covered | T179,T355,T448 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T432,T178,T430 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_11.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_11.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T403,T178,T179 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T179,T180,T355 |
1 | 0 | Covered | T179,T180,T355 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T403,T178,T179 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_12.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_12.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T178,T179,T434 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T178,T179,T180 |
1 | 0 | Covered | T178,T179,T434 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T178,T179,T434 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_13.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_13.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T432,T178,T421 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T179,T180,T354 |
1 | 0 | Covered | T432,T420,T697 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T432,T178,T421 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_14.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_14.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T435,T403,T406 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T178,T179,T354 |
1 | 0 | Covered | T403,T406,T178 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T435,T403,T406 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_15.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_regwen_15.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T403,T178,T611 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T179,T180,T355 |
1 | 0 | Covered | T417,T179,T180 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T403,T178,T611 |