Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sensor_ctrl_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.41 100.00 69.65 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg 92.41 100.00 69.65 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.41 100.00 69.65 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.49 90.31 82.78 92.86 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.83 91.75 86.00 76.41 100.00 100.00 u_sensor_ctrl_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_en_0 100.00 100.00 100.00 100.00
u_alert_en_1 100.00 100.00 100.00 100.00
u_alert_en_10 100.00 100.00 100.00 100.00
u_alert_en_2 100.00 100.00 100.00 100.00
u_alert_en_3 100.00 100.00 100.00 100.00
u_alert_en_4 100.00 100.00 100.00 100.00
u_alert_en_5 100.00 100.00 100.00 100.00
u_alert_en_6 100.00 100.00 100.00 100.00
u_alert_en_7 100.00 100.00 100.00 100.00
u_alert_en_8 100.00 100.00 100.00 100.00
u_alert_en_9 100.00 100.00 100.00 100.00
u_alert_test_fatal_alert 100.00 100.00
u_alert_test_recov_alert 100.00 100.00
u_alert_trig_val_0 100.00 100.00 100.00 100.00
u_alert_trig_val_1 100.00 100.00 100.00 100.00
u_alert_trig_val_10 100.00 100.00 100.00 100.00
u_alert_trig_val_2 100.00 100.00 100.00 100.00
u_alert_trig_val_3 100.00 100.00 100.00 100.00
u_alert_trig_val_4 100.00 100.00 100.00 100.00
u_alert_trig_val_5 100.00 100.00 100.00 100.00
u_alert_trig_val_6 100.00 100.00 100.00 100.00
u_alert_trig_val_7 100.00 100.00 100.00 100.00
u_alert_trig_val_8 100.00 100.00 100.00 100.00
u_alert_trig_val_9 100.00 100.00 100.00 100.00
u_cfg_regwen 51.48 44.44 50.00 60.00
u_chk 100.00 100.00 100.00
u_fatal_alert_en_val_0 96.30 88.89 100.00 100.00
u_fatal_alert_en_val_1 100.00 100.00 100.00 100.00
u_fatal_alert_en_val_10 96.30 88.89 100.00 100.00
u_fatal_alert_en_val_2 96.30 88.89 100.00 100.00
u_fatal_alert_en_val_3 100.00 100.00 100.00 100.00
u_fatal_alert_en_val_4 100.00 100.00 100.00 100.00
u_fatal_alert_en_val_5 96.30 88.89 100.00 100.00
u_fatal_alert_en_val_6 96.30 88.89 100.00 100.00
u_fatal_alert_en_val_7 96.30 88.89 100.00 100.00
u_fatal_alert_en_val_8 96.30 88.89 100.00 100.00
u_fatal_alert_en_val_9 96.30 88.89 100.00 100.00
u_fatal_alert_val_0 47.78 33.33 50.00 60.00
u_fatal_alert_val_1 96.30 88.89 100.00 100.00
u_fatal_alert_val_10 47.78 33.33 50.00 60.00
u_fatal_alert_val_11 96.30 88.89 100.00 100.00
u_fatal_alert_val_2 47.78 33.33 50.00 60.00
u_fatal_alert_val_3 96.30 88.89 100.00 100.00
u_fatal_alert_val_4 96.30 88.89 100.00 100.00
u_fatal_alert_val_5 47.78 33.33 50.00 60.00
u_fatal_alert_val_6 47.78 33.33 50.00 60.00
u_fatal_alert_val_7 47.78 33.33 50.00 60.00
u_fatal_alert_val_8 47.78 33.33 50.00 60.00
u_fatal_alert_val_9 47.78 33.33 50.00 60.00
u_intr_enable_init_status_change 100.00 100.00 100.00 100.00
u_intr_enable_io_status_change 100.00 100.00 100.00 100.00
u_intr_state_init_status_change 100.00 100.00 100.00 100.00
u_intr_state_io_status_change 100.00 100.00 100.00 100.00
u_intr_test_init_status_change 100.00 100.00
u_intr_test_io_status_change 100.00 100.00
u_manual_pad_attr_0 80.00 80.00
u_manual_pad_attr_1 80.00 80.00
u_manual_pad_attr_2 80.00 80.00
u_manual_pad_attr_3 80.00 80.00
u_manual_pad_attr_regwen_0 51.48 44.44 50.00 60.00
u_manual_pad_attr_regwen_1 51.48 44.44 50.00 60.00
u_manual_pad_attr_regwen_2 51.48 44.44 50.00 60.00
u_manual_pad_attr_regwen_3 51.48 44.44 50.00 60.00
u_prim_reg_we_check 100.00 100.00
u_recov_alert_val_0 100.00 100.00 100.00 100.00
u_recov_alert_val_1 100.00 100.00 100.00 100.00
u_recov_alert_val_10 100.00 100.00 100.00 100.00
u_recov_alert_val_2 100.00 100.00 100.00 100.00
u_recov_alert_val_3 100.00 100.00 100.00 100.00
u_recov_alert_val_4 100.00 100.00 100.00 100.00
u_recov_alert_val_5 100.00 100.00 100.00 100.00
u_recov_alert_val_6 100.00 100.00 100.00 100.00
u_recov_alert_val_7 100.00 100.00 100.00 100.00
u_recov_alert_val_8 100.00 100.00 100.00 100.00
u_recov_alert_val_9 100.00 100.00 100.00 100.00
u_reg_if 89.30 94.29 76.54 86.36 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_status_ast_init_done 62.59 77.78 50.00 60.00
u_status_io_pok 62.59 77.78 50.00 60.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sensor_ctrl_reg_top
Line No.TotalCoveredPercent
TOTAL272272100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN40411100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN43511100.00
CONT_ASSIGN44111100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN80711100.00
CONT_ASSIGN83911100.00
CONT_ASSIGN87111100.00
CONT_ASSIGN90311100.00
CONT_ASSIGN93511100.00
CONT_ASSIGN96711100.00
CONT_ASSIGN99911100.00
CONT_ASSIGN103111100.00
CONT_ASSIGN106311100.00
CONT_ASSIGN109511100.00
CONT_ASSIGN112711100.00
CONT_ASSIGN115911100.00
CONT_ASSIGN226111100.00
CONT_ASSIGN226411100.00
CONT_ASSIGN227811100.00
CONT_ASSIGN228511100.00
CONT_ASSIGN228811100.00
CONT_ASSIGN230211100.00
CONT_ASSIGN230911100.00
CONT_ASSIGN231211100.00
CONT_ASSIGN232611100.00
CONT_ASSIGN233311100.00
CONT_ASSIGN233611100.00
CONT_ASSIGN235011100.00
ALWAYS23563030100.00
CONT_ASSIGN238811100.00
ALWAYS239211100.00
CONT_ASSIGN242511100.00
CONT_ASSIGN242711100.00
CONT_ASSIGN242911100.00
CONT_ASSIGN243011100.00
CONT_ASSIGN243211100.00
CONT_ASSIGN243411100.00
CONT_ASSIGN243511100.00
CONT_ASSIGN243711100.00
CONT_ASSIGN243911100.00
CONT_ASSIGN244011100.00
CONT_ASSIGN244211100.00
CONT_ASSIGN244411100.00
CONT_ASSIGN244511100.00
CONT_ASSIGN244711100.00
CONT_ASSIGN244811100.00
CONT_ASSIGN245011100.00
CONT_ASSIGN245211100.00
CONT_ASSIGN245411100.00
CONT_ASSIGN245611100.00
CONT_ASSIGN245811100.00
CONT_ASSIGN246011100.00
CONT_ASSIGN246211100.00
CONT_ASSIGN246411100.00
CONT_ASSIGN246611100.00
CONT_ASSIGN246811100.00
CONT_ASSIGN247011100.00
CONT_ASSIGN247111100.00
CONT_ASSIGN247311100.00
CONT_ASSIGN247411100.00
CONT_ASSIGN247611100.00
CONT_ASSIGN247711100.00
CONT_ASSIGN247911100.00
CONT_ASSIGN248011100.00
CONT_ASSIGN248211100.00
CONT_ASSIGN248311100.00
CONT_ASSIGN248511100.00
CONT_ASSIGN248611100.00
CONT_ASSIGN248811100.00
CONT_ASSIGN248911100.00
CONT_ASSIGN249111100.00
CONT_ASSIGN249211100.00
CONT_ASSIGN249411100.00
CONT_ASSIGN249511100.00
CONT_ASSIGN249711100.00
CONT_ASSIGN249811100.00
CONT_ASSIGN250011100.00
CONT_ASSIGN250111100.00
CONT_ASSIGN250311100.00
CONT_ASSIGN250411100.00
CONT_ASSIGN250611100.00
CONT_ASSIGN250811100.00
CONT_ASSIGN251011100.00
CONT_ASSIGN251211100.00
CONT_ASSIGN251411100.00
CONT_ASSIGN251611100.00
CONT_ASSIGN251811100.00
CONT_ASSIGN252011100.00
CONT_ASSIGN252211100.00
CONT_ASSIGN252411100.00
CONT_ASSIGN252611100.00
CONT_ASSIGN252711100.00
CONT_ASSIGN252911100.00
CONT_ASSIGN253111100.00
CONT_ASSIGN253311100.00
CONT_ASSIGN253511100.00
CONT_ASSIGN253711100.00
CONT_ASSIGN253911100.00
CONT_ASSIGN254111100.00
CONT_ASSIGN254311100.00
CONT_ASSIGN254511100.00
CONT_ASSIGN254711100.00
CONT_ASSIGN254911100.00
CONT_ASSIGN255011100.00
CONT_ASSIGN255211100.00
CONT_ASSIGN255311100.00
CONT_ASSIGN255511100.00
CONT_ASSIGN255611100.00
CONT_ASSIGN255811100.00
CONT_ASSIGN255911100.00
CONT_ASSIGN256111100.00
CONT_ASSIGN256211100.00
CONT_ASSIGN256311100.00
CONT_ASSIGN256511100.00
CONT_ASSIGN256611100.00
CONT_ASSIGN256711100.00
CONT_ASSIGN256911100.00
CONT_ASSIGN257011100.00
CONT_ASSIGN257111100.00
CONT_ASSIGN257311100.00
CONT_ASSIGN257411100.00
CONT_ASSIGN257511100.00
CONT_ASSIGN257711100.00
ALWAYS25813030100.00
ALWAYS26157777100.00
CONT_ASSIGN279000
CONT_ASSIGN279811100.00
CONT_ASSIGN279911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' or '../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
404 1 1
419 1 1
435 1 1
441 1 1
456 1 1
472 1 1
807 1 1
839 1 1
871 1 1
903 1 1
935 1 1
967 1 1
999 1 1
1031 1 1
1063 1 1
1095 1 1
1127 1 1
1159 1 1
2261 1 1
2264 1 1
2278 1 1
2285 1 1
2288 1 1
2302 1 1
2309 1 1
2312 1 1
2326 1 1
2333 1 1
2336 1 1
2350 1 1
2356 1 1
2357 1 1
2358 1 1
2359 1 1
2360 1 1
2361 1 1
2362 1 1
2363 1 1
2364 1 1
2365 1 1
2366 1 1
2367 1 1
2368 1 1
2369 1 1
2370 1 1
2371 1 1
2372 1 1
2373 1 1
2374 1 1
2375 1 1
2376 1 1
2377 1 1
2378 1 1
2379 1 1
2380 1 1
2381 1 1
2382 1 1
2383 1 1
2384 1 1
2385 1 1
2388 1 1
2392 1 1
2425 1 1
2427 1 1
2429 1 1
2430 1 1
2432 1 1
2434 1 1
2435 1 1
2437 1 1
2439 1 1
2440 1 1
2442 1 1
2444 1 1
2445 1 1
2447 1 1
2448 1 1
2450 1 1
2452 1 1
2454 1 1
2456 1 1
2458 1 1
2460 1 1
2462 1 1
2464 1 1
2466 1 1
2468 1 1
2470 1 1
2471 1 1
2473 1 1
2474 1 1
2476 1 1
2477 1 1
2479 1 1
2480 1 1
2482 1 1
2483 1 1
2485 1 1
2486 1 1
2488 1 1
2489 1 1
2491 1 1
2492 1 1
2494 1 1
2495 1 1
2497 1 1
2498 1 1
2500 1 1
2501 1 1
2503 1 1
2504 1 1
2506 1 1
2508 1 1
2510 1 1
2512 1 1
2514 1 1
2516 1 1
2518 1 1
2520 1 1
2522 1 1
2524 1 1
2526 1 1
2527 1 1
2529 1 1
2531 1 1
2533 1 1
2535 1 1
2537 1 1
2539 1 1
2541 1 1
2543 1 1
2545 1 1
2547 1 1
2549 1 1
2550 1 1
2552 1 1
2553 1 1
2555 1 1
2556 1 1
2558 1 1
2559 1 1
2561 1 1
2562 1 1
2563 1 1
2565 1 1
2566 1 1
2567 1 1
2569 1 1
2570 1 1
2571 1 1
2573 1 1
2574 1 1
2575 1 1
2577 1 1
2581 1 1
2582 1 1
2583 1 1
2584 1 1
2585 1 1
2586 1 1
2587 1 1
2588 1 1
2589 1 1
2590 1 1
2591 1 1
2592 1 1
2593 1 1
2594 1 1
2595 1 1
2596 1 1
2597 1 1
2598 1 1
2599 1 1
2600 1 1
2601 1 1
2602 1 1
2603 1 1
2604 1 1
2605 1 1
2606 1 1
2607 1 1
2608 1 1
2609 1 1
2610 1 1
2615 1 1
2616 1 1
2618 1 1
2619 1 1
2623 1 1
2624 1 1
2628 1 1
2629 1 1
2633 1 1
2634 1 1
2638 1 1
2642 1 1
2643 1 1
2644 1 1
2645 1 1
2646 1 1
2647 1 1
2648 1 1
2649 1 1
2650 1 1
2651 1 1
2652 1 1
2656 1 1
2660 1 1
2664 1 1
2668 1 1
2672 1 1
2676 1 1
2680 1 1
2684 1 1
2688 1 1
2692 1 1
2696 1 1
2700 1 1
2701 1 1
2702 1 1
2703 1 1
2704 1 1
2705 1 1
2706 1 1
2707 1 1
2708 1 1
2709 1 1
2710 1 1
2714 1 1
2715 1 1
2716 1 1
2717 1 1
2718 1 1
2719 1 1
2720 1 1
2721 1 1
2722 1 1
2723 1 1
2724 1 1
2728 1 1
2729 1 1
2730 1 1
2731 1 1
2732 1 1
2733 1 1
2734 1 1
2735 1 1
2736 1 1
2737 1 1
2738 1 1
2739 1 1
2743 1 1
2744 1 1
2748 1 1
2752 1 1
2756 1 1
2760 1 1
2764 1 1
2768 1 1
2772 1 1
2776 1 1
2790 unreachable
2798 1 1
2799 1 1


Cond Coverage for Module : sensor_ctrl_reg_top
TotalCoveredPercent
Conditions36925769.65
Logical36925769.65
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T175,T159

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT242,T295,T296
10Not Covered

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT242,T295,T296
010Not Covered
100CoveredT242,T295,T296

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100Not Covered

 LINE       807
 EXPRESSION (alert_en_0_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T159,T160

 LINE       839
 EXPRESSION (alert_en_1_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T159,T160

 LINE       871
 EXPRESSION (alert_en_2_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T159,T160

 LINE       903
 EXPRESSION (alert_en_3_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T159,T160

 LINE       935
 EXPRESSION (alert_en_4_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T159,T160

 LINE       967
 EXPRESSION (alert_en_5_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T159,T160

 LINE       999
 EXPRESSION (alert_en_6_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T159,T160

 LINE       1031
 EXPRESSION (alert_en_7_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T159,T160

 LINE       1063
 EXPRESSION (alert_en_8_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T159,T160

 LINE       1095
 EXPRESSION (alert_en_9_we & cfg_regwen_qs)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T159,T160

 LINE       1127
 EXPRESSION (alert_en_10_we & cfg_regwen_qs)
             -------1------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T159,T160

 LINE       1159
 EXPRESSION (fatal_alert_en_we & cfg_regwen_qs)
             --------1--------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT162,T163,T149

 LINE       2264
 EXPRESSION (manual_pad_attr_0_we & manual_pad_attr_regwen_0_qs)
             ----------1---------   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT28,T29,T30

 LINE       2288
 EXPRESSION (manual_pad_attr_1_we & manual_pad_attr_regwen_1_qs)
             ----------1---------   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT28,T29,T30

 LINE       2312
 EXPRESSION (manual_pad_attr_2_we & manual_pad_attr_regwen_2_qs)
             ----------1---------   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT28,T29,T30

 LINE       2336
 EXPRESSION (manual_pad_attr_3_we & manual_pad_attr_regwen_3_qs)
             ----------1---------   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT28,T29,T30

 LINE       2357
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_STATE_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2358
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_ENABLE_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2359
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_TEST_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2360
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TEST_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2361
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_CFG_REGWEN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2362
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TRIG_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2363
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_0_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2364
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_1_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2365
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_2_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2366
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_3_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2367
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_4_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2368
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_5_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2369
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_6_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2370
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_7_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2371
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_8_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2372
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_9_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2373
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_10_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2374
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_EN_OFFSET)
            ----------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2375
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_RECOV_ALERT_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2376
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2377
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_STATUS_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2378
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_0_OFFSET)
            ---------------------------------------1--------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2379
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_1_OFFSET)
            ---------------------------------------1--------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2380
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_2_OFFSET)
            ---------------------------------------1--------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2381
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_3_OFFSET)
            ---------------------------------------1--------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2382
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_0_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2383
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_1_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2384
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_2_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2385
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_3_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2388
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       2388
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T175,T159
10CoveredT1,T2,T3

 LINE       2392
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT16,T175,T159
11Not Covered

 LINE       2392
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT1,T2,T3
29 (addr_hit[28] & ((|(4'...Not Covered
28 (addr_hit[27] & ((|(4'...Not Covered
27 (addr_hit[26] & ((|(4'...Not Covered
26 (addr_hit[25] & ((|(4'...Not Covered
25 (addr_hit[24] & ((|(4'...Not Covered
24 (addr_hit[23] & ((|(4'...Not Covered
23 (addr_hit[22] & ((|(4'...Not Covered
22 (addr_hit[21] & ((|(4'...Not Covered
21 (addr_hit[20] & ((|(4'...Not Covered
20 (addr_hit[19] & ((|(4'...CoveredT28,T29,T30
19 (addr_hit[18] & ((|(4'...CoveredT28,T29,T30
18 (addr_hit[17] & ((|(4'...CoveredT28,T29,T30
17 (addr_hit[16] & ((|(4'...Not Covered
16 (addr_hit[15] & ((|(4'...Not Covered
15 (addr_hit[14] & ((|(4'...Not Covered
14 (addr_hit[13] & ((|(4'...Not Covered
13 (addr_hit[12] & ((|(4'...Not Covered
12 (addr_hit[11] & ((|(4'...Not Covered
11 (addr_hit[10] & ((|(4'...Not Covered
10 (addr_hit[9] & ((|(4'b...Not Covered
9 (addr_hit[8] & ((|(4'b...Not Covered
8 (addr_hit[7] & ((|(4'b...Not Covered
7 (addr_hit[6] & ((|(4'b...Not Covered
6 (addr_hit[5] & ((|(4'b...CoveredT28,T29,T30
5 (addr_hit[4] & ((|(4'b...Not Covered
4 (addr_hit[3] & ((|(4'b...Not Covered
3 (addr_hit[2] & ((|(4'b...Not Covered
2 (addr_hit[1] & ((|(4'b...Not Covered
1 (addr_hit[0] & ((|(4'b...CoveredT1,T2,T3

 LINE       2392
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       2392
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT28,T29,T30

 LINE       2392
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT28,T29,T30

 LINE       2392
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT28,T29,T30

 LINE       2392
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT28,T29,T30

 LINE       2392
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       2425
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT175,T293,T136

 LINE       2430
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT175,T293,T136

 LINE       2435
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT136,T137,T138

 LINE       2440
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT76,T100,T101

 LINE       2445
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2448
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT16,T159,T160

 LINE       2471
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT16,T159,T160

 LINE       2474
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT16,T159,T160

 LINE       2477
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT16,T159,T160

 LINE       2480
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT16,T159,T160

 LINE       2483
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT16,T159,T160

 LINE       2486
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT16,T159,T160

 LINE       2489
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT16,T159,T160

 LINE       2492
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT16,T159,T160

 LINE       2495
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT16,T159,T160

 LINE       2498
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT16,T159,T160

 LINE       2501
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT16,T159,T160

 LINE       2504
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT162,T163,T149

 LINE       2527
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT16,T159,T174

 LINE       2550
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2553
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2556
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2559
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2562
 EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2563
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT28,T29,T30

 LINE       2566
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2567
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT28,T29,T30

 LINE       2570
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2571
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT28,T29,T30

 LINE       2574
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       2575
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT16,T175,T159
101CoveredT1,T2,T3
110Not Covered
111CoveredT28,T29,T30

Branch Coverage for Module : sensor_ctrl_reg_top
Line No.TotalCoveredPercent
Branches 35 35 100.00
TERNARY 2388 2 2 100.00
IF 68 3 3 100.00
CASE 2616 30 30 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' or '../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 2388 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T242,T295,T296
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 2616 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
addr_hit[28] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : sensor_ctrl_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 94538963 3189 0 0
reAfterRv 94538963 3189 0 0
rePulse 94538963 2407 0 0
wePulse 94538963 782 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 94538963 3189 0 0
T1 59565 2 0 0
T2 18839 1 0 0
T3 58425 1 0 0
T4 277094 0 0 0
T31 126935 5 0 0
T32 70194 2 0 0
T44 300199 2 0 0
T92 35953 2 0 0
T95 548553 1 0 0
T103 0 1 0 0
T115 19772 1 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 94538963 3189 0 0
T1 59565 2 0 0
T2 18839 1 0 0
T3 58425 1 0 0
T4 277094 0 0 0
T31 126935 5 0 0
T32 70194 2 0 0
T44 300199 2 0 0
T92 35953 2 0 0
T95 548553 1 0 0
T103 0 1 0 0
T115 19772 1 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 94538963 2407 0 0
T1 59565 2 0 0
T2 18839 1 0 0
T3 58425 1 0 0
T4 277094 0 0 0
T31 126935 5 0 0
T32 70194 2 0 0
T44 300199 2 0 0
T92 35953 2 0 0
T95 548553 1 0 0
T103 0 1 0 0
T115 19772 1 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 94538963 782 0 0
T6 78758 0 0 0
T10 58131 0 0 0
T16 154426 80 0 0
T45 298014 0 0 0
T50 13766 0 0 0
T52 0 80 0 0
T75 130259 0 0 0
T81 32264 0 0 0
T98 185949 0 0 0
T132 53135 0 0 0
T133 58413 0 0 0
T159 0 55 0 0
T160 0 28 0 0
T161 0 55 0 0
T174 0 1 0 0
T175 0 12 0 0
T291 0 1 0 0
T350 0 28 0 0
T351 0 28 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%