Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	90.68		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T61,T229,T230	Yes	T61,T229,T230	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T1,T210,T211	Yes	T1,T210,T211	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T210,T211	Yes	T1,T210,T211	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T46,T65,T66	Yes	T46,T65,T66	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T231,T232,T61	Yes	T231,T232,T61	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T231,T232,T61	Yes	T231,T232,T61	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T1,T32,T187	Yes	T1,T32,T187	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T46,T47,T73	Yes	T46,T47,T73	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T46,T47,T73	Yes	T46,T47,T73	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T46,T47,T73	Yes	T46,T47,T73	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T46,T47,T73	Yes	T46,T47,T73	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T46,T47,T73	Yes	T46,T47,T73	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T46,T47,T73	Yes	T46,T47,T73	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T46,*T47,*T73	Yes	T46,T47,T73	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T46,T47,T73	Yes	T46,T47,T73	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T61,*T63,*T67	Yes	T61,T63,T67	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T64,T71,T72	Yes	T64,T71,T72	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T64,T71,T72	Yes	T64,T71,T72	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T64,T71,T72	Yes	T64,T71,T72	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T64,T71,T72	Yes	T64,T71,T72	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T64,T71,T72	Yes	T64,T71,T72	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T64,*T71,*T72	Yes	T64,T71,T72	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T64,T71,T72	Yes	T64,T71,T72	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T32	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T64,T71,T72	Yes	T64,T71,T72	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T64,T71,T72	Yes	T64,T71,T72	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T31,T32	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T64,*T71,*T72	Yes	T64,T71,T72	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T31,T32	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T64,T71,T72	Yes	T64,T71,T72	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T5,T66,T93	Yes	T5,T66,T93	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T76,T100,T101	Yes	T76,T100,T101	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T381,T382,T257	Yes	T381,T382,T257	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T381,T382,T257	Yes	T381,T382,T257	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T76,T100,T101	Yes	T76,T100,T101	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T381,T382,T257	Yes	T381,T382,T257	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	T61,*T63,*T67	Yes	T61,T63,T67	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T381,T382,T257	Yes	T381,T382,T257	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T381,T382,T257	Yes	T381,T382,T257	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T381,T382,T257	Yes	T381,T382,T257	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T61,T63,T67	Yes	T76,T100,T101	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T381,T382,T257	Yes	T381,T382,T257	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T257,*T383,*T384	Yes	T381,T382,T257	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T381,T382,T257	Yes	T381,T382,T257	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T46,*T64,*T65	Yes	T46,T64,T65	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T46,T65,T66	Yes	T46,T65,T66	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T32,T210,T303	Yes	T32,T210,T303	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T46,*T64,*T65	Yes	T46,T64,T65	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T31,T10,T11	Yes	T31,T10,T11	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T10,T11,T139	Yes	T10,T11,T139	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T10,T11	Yes	T31,T10,T11	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T31,T10,T11	Yes	T31,T10,T11	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T10,T11,T139	Yes	T10,T11,T139	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T31,T10,T11	Yes	T31,T10,T11	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T10,T12,T194	Yes	T10,T12,T194	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T31,T10,T11	Yes	T31,T10,T11	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T31,T10,T11	Yes	T31,T10,T11	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T11,T370	Yes	T10,T11,T370	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T10,T11	Yes	T31,T10,T11	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T11,T370	Yes	T10,T11,T370	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T31,*T10,*T11	Yes	T31,T10,T11	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T31,T10,T11	Yes	T31,T10,T11	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T31,T282,T369	Yes	T31,T282,T369	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T370,T76,T371	Yes	T370,T76,T371	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T282,T369	Yes	T31,T282,T369	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T31,T282,T369	Yes	T31,T282,T369	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T370,T76,T371	Yes	T370,T76,T371	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T31,T282,T369	Yes	T31,T282,T369	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T31,T282,T369	Yes	T31,T282,T369	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T31,T282,T369	Yes	T31,T282,T369	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T370,T371,T34	Yes	T370,T371,T34	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T282,T369	Yes	T31,T282,T369	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T370,T371,T34	Yes	T370,T371,T34	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T31,*T282,*T369	Yes	T31,T282,T369	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T31,T282,T369	Yes	T31,T282,T369	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T31,T16,T17	Yes	T31,T16,T17	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T31,T16,T17	Yes	T31,T16,T17	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T16,T17	Yes	T31,T16,T17	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T31,T16,T17	Yes	T31,T16,T17	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T31,T16,T17	Yes	T31,T16,T17	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T31,T16,T17	Yes	T31,T16,T17	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T31,T16,T17	Yes	T31,T16,T17	INPUT
tl_usbdev_i.d_error	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T31,T18,T282	Yes	T31,T18,T282	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T18,T282	Yes	T31,T18,T282	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T31,T16,T17	Yes	T31,T16,T17	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T31,*T16,*T17	Yes	T31,T16,T17	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T31,T16,T17	Yes	T31,T16,T17	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T32	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T44,T31	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T65,T61,T63	Yes	T65,T61,T63	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T65,T61,T63	Yes	T65,T61,T63	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T65,T61,T63	Yes	T65,T61,T63	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T65,T61,T63	Yes	T65,T61,T63	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T65,T61,T63	Yes	T65,T61,T63	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T65,T61,T63	Yes	T65,T61,T63	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T65,T61,T63	Yes	T65,T61,T63	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T65,T61,T62	Yes	T65,T61,T62	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T61,T62,T63	Yes	T61,T63,T67	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T65,T61,T62	Yes	T65,T61,T63	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T65,T61,T62	Yes	T65,T61,T63	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T65,T61,T63	Yes	T65,T61,T63	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T65,T61,*T62	Yes	T65,T61,T63	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T63,T67	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T65,T61,T63	Yes	T65,T61,T63	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T3,T44	Yes	T1,T3,T44	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T32	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T44,T31	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T314,T337,T683	Yes	T314,T337,T683	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	INPUT
tl_hmac_i.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	INPUT
tl_hmac_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T44,*T4,*T45	Yes	T44,T4,T45	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T98,T188,T68	Yes	T98,T188,T68	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T91,T98,T188	Yes	T91,T98,T188	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T91,T98,T188	Yes	T91,T98,T188	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T188,T68,T189	Yes	T188,T68,T189	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T91,T98,T188	Yes	T91,T98,T188	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T188,T189,T190	Yes	T188,T189,T190	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T91,T98,T188	Yes	T91,T98,T188	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T91,T98,T188	Yes	T91,T98,T188	INPUT
tl_kmac_i.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T91,T98,T188	Yes	T91,T98,T188	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T91,T98,T188	Yes	T91,T98,T188	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T91,T98,T188	Yes	T188,T68,T189	INPUT
tl_kmac_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T91,*T98,*T188	Yes	T188,T68,T189	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T91,T98,T188	Yes	T91,T98,T188	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T378,T91,T252	Yes	T378,T91,T252	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T378,T91,T252	Yes	T378,T91,T252	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T378,T91,T252	Yes	T378,T91,T252	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T378,T91,T252	Yes	T378,T91,T252	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T378,T91,T252	Yes	T378,T91,T252	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T46,*T65,*T231	Yes	T46,T65,T231	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T378,T91,T252	Yes	T378,T91,T252	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T378,T91,T252	Yes	T378,T91,T252	INPUT
tl_aes_i.d_error	Yes	Yes	T61,T67,T364	Yes	T61,T67,T364	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T378,T91,T252	Yes	T378,T91,T252	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T378,T91,T252	Yes	T378,T91,T252	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T378,T252,T225	Yes	T378,T91,T252	INPUT
tl_aes_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T62,T63	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T46,*T65,*T231	Yes	T46,T65,T231	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T63,T67	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T378,*T91,*T252	Yes	T378,T91,T252	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T378,T91,T252	Yes	T378,T91,T252	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T61,T62,T63	Yes	T61,T63,T67	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T44,T95	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T44,T31	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T62	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T95,*T91,*T132	Yes	T44,T95,T91	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T46,*T65,*T231	Yes	T46,T65,T231	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T95,T31	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T46,*T65,*T231	Yes	T46,T65,T231	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T95,*T91,*T132	Yes	T95,T91,T132	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T95,T31	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T95,T31	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T95,*T91,*T132	Yes	T95,T91,T132	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T95,T31	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	INPUT
tl_edn1_i.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	INPUT
tl_edn1_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T95,*T91,*T132	Yes	T95,T91,T132	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T95,T91,T132	Yes	T95,T91,T132	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T61,*T63,*T67	Yes	T61,T63,T67	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T61,*T63,*T67	Yes	T61,T63,T67	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T44,T95	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T44,T95,T4	Yes	T44,T95,T4	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T95,T4	Yes	T44,T95,T4	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T44,T95,T4	Yes	T44,T95,T4	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T44,T95,T4	Yes	T44,T95,T4	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T44,T95,T4	Yes	T44,T95,T4	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T66,*T425,*T232	Yes	T66,T425,T232	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T44,T95,T4	Yes	T44,T95,T4	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T44,T95,T4	Yes	T44,T95,T4	INPUT
tl_otbn_i.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T44,T95,T4	Yes	T44,T95,T4	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T95,T4	Yes	T44,T95,T4	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T44,T95,T4	Yes	T44,T95,T4	INPUT
tl_otbn_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T66,*T425,*T232	Yes	T66,T425,T232	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T44,*T95,*T4	Yes	T44,T95,T4	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T44,T95,T4	Yes	T44,T95,T4	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T44,T31	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T44,T91,T45	Yes	T44,T91,T45	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T91,T45	Yes	T44,T91,T45	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T44,T91,T45	Yes	T44,T91,T45	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T44,T91,T98	Yes	T44,T91,T98	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T44,T91,T45	Yes	T44,T91,T45	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T44,T91,T45	Yes	T44,T91,T45	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T44,T91,T45	Yes	T44,T91,T45	INPUT
tl_keymgr_i.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T91,T98,T189	Yes	T91,T98,T189	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T91,T45	Yes	T44,T91,T45	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T44,T91,T45	Yes	T44,T91,T45	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T65,*T61,*T63	Yes	T65,T61,T63	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T44,*T91,*T45	Yes	T44,T91,T45	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T44,T91,T45	Yes	T44,T91,T45	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T61,*T63,*T67	Yes	T61,T63,T67	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T44	Yes	T1,T2,T44	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T2,T44	Yes	T1,T2,T44	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T61,*T63,*T67	Yes	T61,T62,T63	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T62,T63	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T44,T31	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T61,*T63,*T67	Yes	T61,T63,T67	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T62,T63	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T146,T289,T290	Yes	T146,T289,T290	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T42,T43	Yes	T44,T4,T45	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T4,T42,T43	Yes	T44,T4,T45	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T62,T63	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T63,T67	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T63,T67	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T142,*T143,*T144	Yes	T223,T424,T142	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T44,T4,T45	Yes	T44,T4,T45	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T32	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range