Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T145,T285,T287
0	1	Covered	T145,T285,T287
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T285,T287
1	Covered	T145,T285,T287

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T285,T287
1	Covered	T145,T285,T287

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T145,T285,T287
1	1	Covered	T145,T285,T287

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T145,T285,T287
1	0	Covered	T145,T285,T287
1	1	Covered	T145,T285,T287

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T145,T285,T287

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T285,T287
0	Covered	T145,T285,T287

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T285,T287
0	Covered	T145,T285,T287

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	763280980	745061812	0	0
CheckNGreaterZero_A	1810	1810	0	0
GntImpliesReady_A	763280980	5376	0	0
GntImpliesValid_A	763280980	5376	0	0
GrantKnown_A	763280980	745061812	0	0
IdxKnown_A	763280980	745061812	0	0
IndexIsCorrect_A	763280980	5376	0	0
NoReadyValidNoGrant_A	763280980	0	0	0
Priority_A	763280980	5376	0	0
ReadyAndValidImplyGrant_A	763280980	5376	0	0
ReqAndReadyImplyGrant_A	763280980	5376	0	0
ReqImpliesValid_A	763280980	5376	0	0
ValidKnown_A	763280980	745061812	0	0
gen_data_port_assertion.DataFlow_A	763280980	5376	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763280980	745061812	0	0
T1	490038	489820	0	0
T2	153836	153712	0	0
T3	483692	483568	0	0
T4	230580	230556	0	0
T31	1041908	1041362	0	0
T32	578602	578354	0	0
T44	249832	249820	0	0
T92	296438	296314	0	0
T95	287162	287152	0	0
T115	161606	161504	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1810	1810	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T31	2	2	0	0
T32	2	2	0	0
T44	2	2	0	0
T92	2	2	0	0
T95	2	2	0	0
T115	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763280980	5376	0	0
T46	334500	0	0	0
T68	502136	0	0	0
T96	583028	0	0	0
T110	1335168	0	0	0
T145	142204	1788	0	0
T188	163970	0	0	0
T225	443132	0	0	0
T239	290558	0	0	0
T252	211760	0	0	0
T285	0	1791	0	0
T287	0	1797	0	0
T288	155110	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763280980	5376	0	0
T46	334500	0	0	0
T68	502136	0	0	0
T96	583028	0	0	0
T110	1335168	0	0	0
T145	142204	1788	0	0
T188	163970	0	0	0
T225	443132	0	0	0
T239	290558	0	0	0
T252	211760	0	0	0
T285	0	1791	0	0
T287	0	1797	0	0
T288	155110	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763280980	745061812	0	0
T1	490038	489820	0	0
T2	153836	153712	0	0
T3	483692	483568	0	0
T4	230580	230556	0	0
T31	1041908	1041362	0	0
T32	578602	578354	0	0
T44	249832	249820	0	0
T92	296438	296314	0	0
T95	287162	287152	0	0
T115	161606	161504	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763280980	745061812	0	0
T1	490038	489820	0	0
T2	153836	153712	0	0
T3	483692	483568	0	0
T4	230580	230556	0	0
T31	1041908	1041362	0	0
T32	578602	578354	0	0
T44	249832	249820	0	0
T92	296438	296314	0	0
T95	287162	287152	0	0
T115	161606	161504	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763280980	5376	0	0
T46	334500	0	0	0
T68	502136	0	0	0
T96	583028	0	0	0
T110	1335168	0	0	0
T145	142204	1788	0	0
T188	163970	0	0	0
T225	443132	0	0	0
T239	290558	0	0	0
T252	211760	0	0	0
T285	0	1791	0	0
T287	0	1797	0	0
T288	155110	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763280980	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763280980	5376	0	0
T46	334500	0	0	0
T68	502136	0	0	0
T96	583028	0	0	0
T110	1335168	0	0	0
T145	142204	1788	0	0
T188	163970	0	0	0
T225	443132	0	0	0
T239	290558	0	0	0
T252	211760	0	0	0
T285	0	1791	0	0
T287	0	1797	0	0
T288	155110	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763280980	5376	0	0
T46	334500	0	0	0
T68	502136	0	0	0
T96	583028	0	0	0
T110	1335168	0	0	0
T145	142204	1788	0	0
T188	163970	0	0	0
T225	443132	0	0	0
T239	290558	0	0	0
T252	211760	0	0	0
T285	0	1791	0	0
T287	0	1797	0	0
T288	155110	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763280980	5376	0	0
T46	334500	0	0	0
T68	502136	0	0	0
T96	583028	0	0	0
T110	1335168	0	0	0
T145	142204	1788	0	0
T188	163970	0	0	0
T225	443132	0	0	0
T239	290558	0	0	0
T252	211760	0	0	0
T285	0	1791	0	0
T287	0	1797	0	0
T288	155110	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763280980	5376	0	0
T46	334500	0	0	0
T68	502136	0	0	0
T96	583028	0	0	0
T110	1335168	0	0	0
T145	142204	1788	0	0
T188	163970	0	0	0
T225	443132	0	0	0
T239	290558	0	0	0
T252	211760	0	0	0
T285	0	1791	0	0
T287	0	1797	0	0
T288	155110	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763280980	745061812	0	0
T1	490038	489820	0	0
T2	153836	153712	0	0
T3	483692	483568	0	0
T4	230580	230556	0	0
T31	1041908	1041362	0	0
T32	578602	578354	0	0
T44	249832	249820	0	0
T92	296438	296314	0	0
T95	287162	287152	0	0
T115	161606	161504	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763280980	5376	0	0
T46	334500	0	0	0
T68	502136	0	0	0
T96	583028	0	0	0
T110	1335168	0	0	0
T145	142204	1788	0	0
T188	163970	0	0	0
T225	443132	0	0	0
T239	290558	0	0	0
T252	211760	0	0	0
T285	0	1791	0	0
T287	0	1797	0	0
T288	155110	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T145,T285,T287
0	1	Covered	T145,T285,T287
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T285,T287
1	Covered	T145,T285,T287

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T285,T287
1	Covered	T145,T285,T287

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T145,T285,T287
1	1	Covered	T145,T285,T287

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T145,T285,T287
1	0	Covered	T145,T285,T287
1	1	Covered	T145,T285,T287

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T145,T285,T287

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T285,T287
0	Covered	T145,T285,T287

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T285,T287
0	Covered	T145,T285,T287

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381640490	372530906	0	0
CheckNGreaterZero_A	905	905	0	0
GntImpliesReady_A	381640490	4386	0	0
GntImpliesValid_A	381640490	4386	0	0
GrantKnown_A	381640490	372530906	0	0
IdxKnown_A	381640490	372530906	0	0
IndexIsCorrect_A	381640490	4386	0	0
NoReadyValidNoGrant_A	381640490	0	0	0
Priority_A	381640490	4386	0	0
ReadyAndValidImplyGrant_A	381640490	4386	0	0
ReqAndReadyImplyGrant_A	381640490	4386	0	0
ReqImpliesValid_A	381640490	4386	0	0
ValidKnown_A	381640490	372530906	0	0
gen_data_port_assertion.DataFlow_A	381640490	4386	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	372530906	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	4386	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	1458	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	1461	0	0
T287	0	1467	0	0
T288	77555	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	4386	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	1458	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	1461	0	0
T287	0	1467	0	0
T288	77555	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	372530906	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	372530906	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	4386	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	1458	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	1461	0	0
T287	0	1467	0	0
T288	77555	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	4386	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	1458	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	1461	0	0
T287	0	1467	0	0
T288	77555	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	4386	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	1458	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	1461	0	0
T287	0	1467	0	0
T288	77555	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	4386	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	1458	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	1461	0	0
T287	0	1467	0	0
T288	77555	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	4386	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	1458	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	1461	0	0
T287	0	1467	0	0
T288	77555	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	372530906	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	4386	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	1458	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	1461	0	0
T287	0	1467	0	0
T288	77555	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T145,T285,T287
0	1	Covered	T145,T285,T287
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T285,T287
1	Covered	T145,T285,T287

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T285,T287
1	Covered	T145,T285,T287

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T145,T285,T287
1	1	Covered	T145,T285,T287

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T145,T285,T287
1	0	Covered	T145,T285,T287
1	1	Covered	T145,T285,T287

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T145,T285,T287

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T285,T287
0	Covered	T145,T285,T287

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T285,T287
0	Covered	T145,T285,T287

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381640490	372530906	0	0
CheckNGreaterZero_A	905	905	0	0
GntImpliesReady_A	381640490	990	0	0
GntImpliesValid_A	381640490	990	0	0
GrantKnown_A	381640490	372530906	0	0
IdxKnown_A	381640490	372530906	0	0
IndexIsCorrect_A	381640490	990	0	0
NoReadyValidNoGrant_A	381640490	0	0	0
Priority_A	381640490	990	0	0
ReadyAndValidImplyGrant_A	381640490	990	0	0
ReqAndReadyImplyGrant_A	381640490	990	0	0
ReqImpliesValid_A	381640490	990	0	0
ValidKnown_A	381640490	372530906	0	0
gen_data_port_assertion.DataFlow_A	381640490	990	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	372530906	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	990	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	330	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	330	0	0
T287	0	330	0	0
T288	77555	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	990	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	330	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	330	0	0
T287	0	330	0	0
T288	77555	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	372530906	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	372530906	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	990	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	330	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	330	0	0
T287	0	330	0	0
T288	77555	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	990	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	330	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	330	0	0
T287	0	330	0	0
T288	77555	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	990	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	330	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	330	0	0
T287	0	330	0	0
T288	77555	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	990	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	330	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	330	0	0
T287	0	330	0	0
T288	77555	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	990	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	330	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	330	0	0
T287	0	330	0	0
T288	77555	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	372530906	0	0
T1	245019	244910	0	0
T2	76918	76856	0	0
T3	241846	241784	0	0
T4	115290	115278	0	0
T31	520954	520681	0	0
T32	289301	289177	0	0
T44	124916	124910	0	0
T92	148219	148157	0	0
T95	143581	143576	0	0
T115	80803	80752	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	990	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	330	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	330	0	0
T287	0	330	0	0
T288	77555	0	0	0