Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	905	905	0	0
OutputsKnown_A	95848855	95294356	0	0
gen_no_flops.OutputDelay_A	95848855	95294356	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95848855	95294356	0	0
T1	60192	59545	0	0
T2	19270	18827	0	0
T3	59234	58413	0	0
T4	278468	277072	0	0
T31	127523	126925	0	0
T32	70588	70171	0	0
T44	300686	300187	0	0
T92	36471	35941	0	0
T95	549012	548542	0	0
T115	20170	19762	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95848855	95294356	0	0
T1	60192	59545	0	0
T2	19270	18827	0	0
T3	59234	58413	0	0
T4	278468	277072	0	0
T31	127523	126925	0	0
T32	70588	70171	0	0
T44	300686	300187	0	0
T92	36471	35941	0	0
T95	549012	548542	0	0
T115	20170	19762	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	905	905	0	0
OutputsKnown_A	95848855	95294356	0	0
gen_no_flops.OutputDelay_A	95848855	95294356	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95848855	95294356	0	0
T1	60192	59545	0	0
T2	19270	18827	0	0
T3	59234	58413	0	0
T4	278468	277072	0	0
T31	127523	126925	0	0
T32	70588	70171	0	0
T44	300686	300187	0	0
T92	36471	35941	0	0
T95	549012	548542	0	0
T115	20170	19762	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95848855	95294356	0	0
T1	60192	59545	0	0
T2	19270	18827	0	0
T3	59234	58413	0	0
T4	278468	277072	0	0
T31	127523	126925	0	0
T32	70588	70171	0	0
T44	300686	300187	0	0
T92	36471	35941	0	0
T95	549012	548542	0	0
T115	20170	19762	0	0