Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : chip_earlgrey_asic
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.90 80.00 100.00 95.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 92.83 80.00 100.00 98.48



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.83 80.00 100.00 98.48


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.52 95.29 93.66 91.79 94.46 97.38


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
top_earlgrey 94.27 95.23 93.18 91.68 94.24 97.02
u_ast 92.94 92.94
u_padring 99.08 99.40 99.80 96.57 99.60 100.00
u_prim_usb_diff_rx 96.30 100.00 88.89 100.00

Line Coverage for Module : chip_earlgrey_asic
Line No.TotalCoveredPercent
TOTAL252080.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN786100.00
CONT_ASSIGN797100.00
CONT_ASSIGN822100.00
CONT_ASSIGN829100.00
CONT_ASSIGN83611100.00
CONT_ASSIGN83911100.00
CONT_ASSIGN84511100.00
CONT_ASSIGN84711100.00
CONT_ASSIGN851100.00
CONT_ASSIGN85411100.00
CONT_ASSIGN101811100.00
CONT_ASSIGN101911100.00
CONT_ASSIGN102011100.00
CONT_ASSIGN102111100.00
CONT_ASSIGN102811100.00
CONT_ASSIGN104511100.00
CONT_ASSIGN104611100.00
CONT_ASSIGN104711100.00
CONT_ASSIGN104811100.00
CONT_ASSIGN105211100.00
CONT_ASSIGN105311100.00
CONT_ASSIGN105411100.00
CONT_ASSIGN105511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
212 1 1
213 1 1
786 0 1
797 0 1
822 0 1
829 0 1
836 1 1
839 1 1
845 1 1
847 1 1
851 0 1
854 1 1
1018 1 1
1019 1 1
1020 1 1
1021 1 1
1028 1 1
1045 1 1
1046 1 1
1047 1 1
1048 1 1
1052 1 1
1053 1 1
1054 1 1
1055 1 1


Cond Coverage for Module : chip_earlgrey_asic
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT103,T104,T16

Toggle Coverage for Module : chip_earlgrey_asic
TotalCoveredPercent
Totals 70 64 91.43
Total Bits 140 134 95.71
Total Bits 0->1 70 70 100.00
Total Bits 1->0 70 64 91.43

Ports 70 64 91.43
Port Bits 140 134 95.71
Port Bits 0->1 70 70 100.00
Port Bits 1->0 70 64 91.43

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
POR_N Yes Yes T4,T5,T6 Yes T1,T2,T3 INOUT
USB_P Yes Yes T18,T22,T23 Yes T18,T22,T23 INOUT
USB_N Yes Yes T18,T22,T23 Yes T18,T22,T23 INOUT
CC1 No No Yes T7,T8,T9 INOUT
CC2 No No Yes T7,T8,T9 INOUT
FLASH_TEST_VOLT No No Yes T7,T8,T9 INOUT
FLASH_TEST_MODE0 No No Yes T7,T8,T9 INOUT
FLASH_TEST_MODE1 No No Yes T7,T8,T9 INOUT
OTP_EXT_VOLT No No Yes T7,T8,T9 INOUT
SPI_HOST_D0 Yes Yes T10,T11,T12 Yes T10,T11,T12 INOUT
SPI_HOST_D1 Yes Yes T10,T11,T12 Yes T10,T11,T12 INOUT
SPI_HOST_D2 Yes Yes T10,T12,T194 Yes T10,T12,T194 INOUT
SPI_HOST_D3 Yes Yes T10,T12,T194 Yes T10,T12,T8 INOUT
SPI_HOST_CLK Yes Yes T10,T11,T12 Yes T10,T11,T12 INOUT
SPI_HOST_CS_L Yes Yes T10,T11,T12 Yes T10,T11,T12 INOUT
SPI_DEV_D0 Yes Yes T10,T11,T177 Yes T10,T11,T177 INOUT
SPI_DEV_D1 Yes Yes T10,T11,T177 Yes T10,T11,T177 INOUT
SPI_DEV_D2 Yes Yes T10,T12,T194 Yes T10,T12,T194 INOUT
SPI_DEV_D3 Yes Yes T10,T12,T194 Yes T10,T12,T194 INOUT
SPI_DEV_CLK Yes Yes T10,T11,T177 Yes T10,T11,T177 INOUT
SPI_DEV_CS_L Yes Yes T10,T11,T177 Yes T10,T11,T177 INOUT
IOR8 Yes Yes T19,T196,T197 Yes T19,T196,T197 INOUT
IOR9 Yes Yes T19,T334,T20 Yes T19,T36,T196 INOUT
IOA0 Yes Yes T13,T14,T15 Yes T13,T14,T15 INOUT
IOA1 Yes Yes T13,T14,T15 Yes T13,T14,T15 INOUT
IOA2 Yes Yes T183,T24,T184 Yes T183,T24,T184 INOUT
IOA3 Yes Yes T24,T25,T26 Yes T24,T25,T26 INOUT
IOA4 Yes Yes T122,T181,T182 Yes T122,T181,T182 INOUT
IOA5 Yes Yes T122,T181,T182 Yes T122,T181,T182 INOUT
IOA6 Yes Yes T24,T25,T26 Yes T24,T25,T26 INOUT
IOA7 Yes Yes T199,T39,T200 Yes T199,T39,T200 INOUT
IOA8 Yes Yes T199,T200,T24 Yes T199,T200,T24 INOUT
IOB0 Yes Yes T34,T35,T28 Yes T34,T35,T9 INOUT
IOB1 Yes Yes T34,T35,T28 Yes T34,T35,T28 INOUT
IOB2 Yes Yes T28,T29,T30 Yes T28,T29,T30 INOUT
IOB3 Yes Yes T19,T196,T197 Yes T19,T196,T197 INOUT
IOB4 Yes Yes T3,T133,T155 Yes T3,T133,T155 INOUT
IOB5 Yes Yes T3,T133,T155 Yes T3,T133,T155 INOUT
IOB6 Yes Yes T19,T196,T25 Yes T19,T196,T25 INOUT
IOB7 Yes Yes T16,T51,T52 Yes T16,T36,T51 INOUT
IOB8 Yes Yes T19,T196,T25 Yes T196,T25,T197 INOUT
IOB9 Yes Yes T2,T19,T202 Yes T2,T202,T203 INOUT
IOB10 Yes Yes T2,T183,T204 Yes T2,T183,T204 INOUT
IOB11 Yes Yes T2,T183,T127 Yes T2,T183,T127 INOUT
IOB12 Yes Yes T2,T183,T127 Yes T2,T183,T127 INOUT
IOC0 Yes Yes T44,T4,T45 Yes T177,T348,T7 INOUT
IOC1 Yes Yes T177,T205,T349 Yes T177,T7,T205 INOUT
IOC2 Yes Yes T177,T205,T349 Yes T177,T7,T205 INOUT
IOC3 Yes Yes T206,T207,T7 Yes T206,T207,T322 INOUT
IOC4 Yes Yes T4,T206,T42 Yes T4,T206,T42 INOUT
IOC5 Yes Yes T50,T110,T47 Yes T50,T110,T47 INOUT
IOC6 Yes Yes T49,T74,T155 Yes T49,T74,T155 INOUT
IOC7 Yes Yes T19,T196,T197 Yes T19,T18,T196 INOUT
IOC8 Yes Yes T50,T110,T47 Yes T110,T47,T73 INOUT
IOC9 Yes Yes T19,T36,T196 Yes T19,T36,T196 INOUT
IOC10 Yes Yes T183,T204,T184 Yes T183,T204,T184 INOUT
IOC11 Yes Yes T183,T204,T184 Yes T183,T204,T184 INOUT
IOC12 Yes Yes T183,T204,T184 Yes T183,T204,T184 INOUT
IOR0 Yes Yes T50,T110,T46 Yes T50,T110,T46 INOUT
IOR1 Yes Yes T50,T46,T108 Yes T50,T46,T108 INOUT
IOR2 Yes Yes T50,T110,T46 Yes T50,T110,T46 INOUT
IOR3 Yes Yes T50,T110,T46 Yes T50,T110,T46 INOUT
IOR4 Yes Yes T110,T46,T47 Yes T49,T50,T110 INOUT
IOR5 Yes Yes T25,T20,T26 Yes T25,T20,T26 INOUT
IOR6 Yes Yes T25,T26,T201 Yes T25,T20,T26 INOUT
IOR7 Yes Yes T25,T26,T201 Yes T25,T26,T7 INOUT
IOR10 Yes Yes T25,T26,T201 Yes T25,T26,T7 INOUT
IOR11 Yes Yes T25,T26,T201 Yes T25,T26,T201 INOUT
IOR12 Yes Yes T25,T26,T201 Yes T25,T26,T201 INOUT
IOR13 Yes Yes T16,T196,T51 Yes T16,T196,T51 INOUT

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL252080.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN786100.00
CONT_ASSIGN797100.00
CONT_ASSIGN822100.00
CONT_ASSIGN829100.00
CONT_ASSIGN83611100.00
CONT_ASSIGN83911100.00
CONT_ASSIGN84511100.00
CONT_ASSIGN84711100.00
CONT_ASSIGN851100.00
CONT_ASSIGN85411100.00
CONT_ASSIGN101811100.00
CONT_ASSIGN101911100.00
CONT_ASSIGN102011100.00
CONT_ASSIGN102111100.00
CONT_ASSIGN102811100.00
CONT_ASSIGN104511100.00
CONT_ASSIGN104611100.00
CONT_ASSIGN104711100.00
CONT_ASSIGN104811100.00
CONT_ASSIGN105211100.00
CONT_ASSIGN105311100.00
CONT_ASSIGN105411100.00
CONT_ASSIGN105511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
212 1 1
213 1 1
786 0 1
797 0 1
822 0 1
829 0 1
836 1 1
839 1 1
845 1 1
847 1 1
851 0 1
854 1 1
1018 1 1
1019 1 1
1020 1 1
1021 1 1
1028 1 1
1045 1 1
1046 1 1
1047 1 1
1048 1 1
1052 1 1
1053 1 1
1054 1 1
1055 1 1


Cond Coverage for Instance : tb.dut
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT103,T104,T16

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 66 64 96.97
Total Bits 132 130 98.48
Total Bits 0->1 66 66 100.00
Total Bits 1->0 66 64 96.97

Ports 66 64 96.97
Port Bits 132 130 98.48
Port Bits 0->1 66 66 100.00
Port Bits 1->0 66 64 96.97

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
POR_N Yes Yes T4,T5,T6 Yes T1,T2,T3 INOUT
USB_P Yes Yes T18,T22,T23 Yes T18,T22,T23 INOUT
USB_N Yes Yes T18,T22,T23 Yes T18,T22,T23 INOUT
CC1 No No Yes T7,T8,T9 INOUT
CC2 No No Yes T7,T8,T9 INOUT
FLASH_TEST_VOLT[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0 Yes Yes T10,T11,T12 Yes T10,T11,T12 INOUT
SPI_HOST_D1 Yes Yes T10,T11,T12 Yes T10,T11,T12 INOUT
SPI_HOST_D2 Yes Yes T10,T12,T194 Yes T10,T12,T194 INOUT
SPI_HOST_D3 Yes Yes T10,T12,T194 Yes T10,T12,T8 INOUT
SPI_HOST_CLK Yes Yes T10,T11,T12 Yes T10,T11,T12 INOUT
SPI_HOST_CS_L Yes Yes T10,T11,T12 Yes T10,T11,T12 INOUT
SPI_DEV_D0 Yes Yes T10,T11,T177 Yes T10,T11,T177 INOUT
SPI_DEV_D1 Yes Yes T10,T11,T177 Yes T10,T11,T177 INOUT
SPI_DEV_D2 Yes Yes T10,T12,T194 Yes T10,T12,T194 INOUT
SPI_DEV_D3 Yes Yes T10,T12,T194 Yes T10,T12,T194 INOUT
SPI_DEV_CLK Yes Yes T10,T11,T177 Yes T10,T11,T177 INOUT
SPI_DEV_CS_L Yes Yes T10,T11,T177 Yes T10,T11,T177 INOUT
IOR8 Yes Yes T19,T196,T197 Yes T19,T196,T197 INOUT
IOR9 Yes Yes T19,T334,T20 Yes T19,T36,T196 INOUT
IOA0 Yes Yes T13,T14,T15 Yes T13,T14,T15 INOUT
IOA1 Yes Yes T13,T14,T15 Yes T13,T14,T15 INOUT
IOA2 Yes Yes T183,T24,T184 Yes T183,T24,T184 INOUT
IOA3 Yes Yes T24,T25,T26 Yes T24,T25,T26 INOUT
IOA4 Yes Yes T122,T181,T182 Yes T122,T181,T182 INOUT
IOA5 Yes Yes T122,T181,T182 Yes T122,T181,T182 INOUT
IOA6 Yes Yes T24,T25,T26 Yes T24,T25,T26 INOUT
IOA7 Yes Yes T199,T39,T200 Yes T199,T39,T200 INOUT
IOA8 Yes Yes T199,T200,T24 Yes T199,T200,T24 INOUT
IOB0 Yes Yes T34,T35,T28 Yes T34,T35,T9 INOUT
IOB1 Yes Yes T34,T35,T28 Yes T34,T35,T28 INOUT
IOB2 Yes Yes T28,T29,T30 Yes T28,T29,T30 INOUT
IOB3 Yes Yes T19,T196,T197 Yes T19,T196,T197 INOUT
IOB4 Yes Yes T3,T133,T155 Yes T3,T133,T155 INOUT
IOB5 Yes Yes T3,T133,T155 Yes T3,T133,T155 INOUT
IOB6 Yes Yes T19,T196,T25 Yes T19,T196,T25 INOUT
IOB7 Yes Yes T16,T51,T52 Yes T16,T36,T51 INOUT
IOB8 Yes Yes T19,T196,T25 Yes T196,T25,T197 INOUT
IOB9 Yes Yes T2,T19,T202 Yes T2,T202,T203 INOUT
IOB10 Yes Yes T2,T183,T204 Yes T2,T183,T204 INOUT
IOB11 Yes Yes T2,T183,T127 Yes T2,T183,T127 INOUT
IOB12 Yes Yes T2,T183,T127 Yes T2,T183,T127 INOUT
IOC0 Yes Yes T44,T4,T45 Yes T177,T348,T7 INOUT
IOC1 Yes Yes T177,T205,T349 Yes T177,T7,T205 INOUT
IOC2 Yes Yes T177,T205,T349 Yes T177,T7,T205 INOUT
IOC3 Yes Yes T206,T207,T7 Yes T206,T207,T322 INOUT
IOC4 Yes Yes T4,T206,T42 Yes T4,T206,T42 INOUT
IOC5 Yes Yes T50,T110,T47 Yes T50,T110,T47 INOUT
IOC6 Yes Yes T49,T74,T155 Yes T49,T74,T155 INOUT
IOC7 Yes Yes T19,T196,T197 Yes T19,T18,T196 INOUT
IOC8 Yes Yes T50,T110,T47 Yes T110,T47,T73 INOUT
IOC9 Yes Yes T19,T36,T196 Yes T19,T36,T196 INOUT
IOC10 Yes Yes T183,T204,T184 Yes T183,T204,T184 INOUT
IOC11 Yes Yes T183,T204,T184 Yes T183,T204,T184 INOUT
IOC12 Yes Yes T183,T204,T184 Yes T183,T204,T184 INOUT
IOR0 Yes Yes T50,T110,T46 Yes T50,T110,T46 INOUT
IOR1 Yes Yes T50,T46,T108 Yes T50,T46,T108 INOUT
IOR2 Yes Yes T50,T110,T46 Yes T50,T110,T46 INOUT
IOR3 Yes Yes T50,T110,T46 Yes T50,T110,T46 INOUT
IOR4 Yes Yes T110,T46,T47 Yes T49,T50,T110 INOUT
IOR5 Yes Yes T25,T20,T26 Yes T25,T20,T26 INOUT
IOR6 Yes Yes T25,T26,T201 Yes T25,T20,T26 INOUT
IOR7 Yes Yes T25,T26,T201 Yes T25,T26,T7 INOUT
IOR10 Yes Yes T25,T26,T201 Yes T25,T26,T7 INOUT
IOR11 Yes Yes T25,T26,T201 Yes T25,T26,T201 INOUT
IOR12 Yes Yes T25,T26,T201 Yes T25,T26,T201 INOUT
IOR13 Yes Yes T16,T196,T51 Yes T16,T196,T51 INOUT

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