Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1952321	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27970896

1

T1

17429

T2

10867

T3

2996

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	20691452	1			T1	7432		T2	4821		T3	464
values[0x0]	7889668	1			T1	9997		T2	6046		T3	2532
values[0x1]	1342097	1			T1	1198		T2	397		T3	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	701608	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29221609

1

T1

18627

T2

11264

T3

3025

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13690621	1			T1	9314		T2	5632		T3	1513
valid_sources[0x01]	13688401	1			T1	9313		T2	5632		T3	1512
valid_sources[0x02]	40486	1			T44	7		T58	1		T166	63
valid_sources[0x03]	41452	1			T58	6		T169	3		T166	87
valid_sources[0x04]	42407	1			T166	40		T642	551		T350	234
valid_sources[0x05]	40427	1			T58	2		T166	54		T642	128
valid_sources[0x06]	40097	1			T58	1		T166	76		T642	256
valid_sources[0x07]	40660	1			T166	58		T642	384		T350	162
valid_sources[0x08]	40556	1			T166	56		T642	640		T350	177
valid_sources[0x09]	40572	1			T166	120		T642	512		T350	161
valid_sources[0x0a]	40964	1			T227	39		T166	90		T642	256
valid_sources[0x0b]	41577	1			T58	7		T169	2		T166	128
valid_sources[0x0c]	41618	1			T166	89		T642	1024		T350	145
valid_sources[0x0d]	41270	1			T166	112		T642	256		T350	157
valid_sources[0x0e]	40590	1			T166	99		T642	384		T350	169
valid_sources[0x0f]	40741	1			T166	99		T642	256		T350	130
valid_sources[0x10]	40391	1			T169	2		T166	68		T642	256
valid_sources[0x11]	42408	1			T166	38		T642	128		T350	175
valid_sources[0x12]	41167	1			T166	120		T642	256		T350	173
valid_sources[0x13]	43596	1			T166	94		T642	128		T350	117
valid_sources[0x14]	40335	1			T166	57		T642	256		T350	95
valid_sources[0x15]	40682	1			T166	125		T642	384		T350	127
valid_sources[0x16]	41362	1			T166	75		T642	128		T350	163
valid_sources[0x17]	40911	1			T412	39		T166	87		T642	256
valid_sources[0x18]	40924	1			T58	1		T166	170		T642	512
valid_sources[0x19]	40666	1			T166	90		T642	128		T350	171
valid_sources[0x1a]	41785	1			T58	3		T166	68		T642	640
valid_sources[0x1b]	40942	1			T166	88		T642	128		T350	165
valid_sources[0x1c]	40608	1			T166	66		T642	512		T350	151
valid_sources[0x1d]	41914	1			T58	5		T169	8		T166	110
valid_sources[0x1e]	40850	1			T44	2		T58	1		T166	112
valid_sources[0x1f]	40991	1			T166	66		T642	256		T350	145
valid_sources[0x20]	40910	1			T166	137		T642	384		T350	223

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19873371

1

T1

7432

T2

4821

T3

464

values[0x0]

all_enables

biggest_size

7847778

1

T1

9997

T2

6046

T3

2532

values[0x1]

all_enables

biggest_size

249747

1

T44

19

T57

22

T58

27

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2754447	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

434899

1

T54

30

T55

4

T56

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1080706	1			T54	61		T55	26		T56	25
values[0x0]	1028310	1			T54	71		T56	24		T59	4896
values[0x1]	1080330	1			T54	59		T55	22		T56	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2133379	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1055967

1

T54

59

T55

14

T56

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51538	1			T54	15		T56	1		T59	188
valid_sources[0x01]	50061	1			T55	1		T59	255		T103	42
valid_sources[0x02]	50049	1			T54	4		T55	3		T59	258
valid_sources[0x03]	51063	1			T59	205		T103	36		T491	15
valid_sources[0x04]	49677	1			T59	248		T103	41		T507	1
valid_sources[0x05]	50159	1			T59	234		T103	34		T507	1
valid_sources[0x06]	49408	1			T54	4		T55	7		T56	1
valid_sources[0x07]	50250	1			T54	7		T55	3		T56	1
valid_sources[0x08]	49725	1			T54	3		T55	2		T56	3
valid_sources[0x09]	50185	1			T54	6		T59	216		T103	33
valid_sources[0x0a]	50043	1			T59	220		T103	39		T491	10
valid_sources[0x0b]	50044	1			T54	1		T59	256		T103	33
valid_sources[0x0c]	49304	1			T55	2		T56	2		T59	249
valid_sources[0x0d]	49943	1			T54	1		T55	1		T56	1
valid_sources[0x0e]	50960	1			T56	2		T59	216		T103	46
valid_sources[0x0f]	49379	1			T59	241		T103	36		T491	22
valid_sources[0x10]	49573	1			T59	228		T103	40		T491	17
valid_sources[0x11]	50988	1			T56	1		T59	256		T103	34
valid_sources[0x12]	50270	1			T56	2		T59	223		T103	30
valid_sources[0x13]	49684	1			T54	5		T59	216		T103	30
valid_sources[0x14]	50211	1			T54	9		T59	214		T103	31
valid_sources[0x15]	49100	1			T54	15		T55	4		T56	3
valid_sources[0x16]	50484	1			T54	16		T55	1		T56	3
valid_sources[0x17]	49646	1			T56	3		T59	219		T103	30
valid_sources[0x18]	50388	1			T56	1		T59	332		T103	41
valid_sources[0x19]	50325	1			T56	2		T59	204		T103	27
valid_sources[0x1a]	48979	1			T59	247		T103	40		T491	17
valid_sources[0x1b]	49863	1			T56	3		T59	291		T103	40
valid_sources[0x1c]	49026	1			T59	233		T103	45		T507	1
valid_sources[0x1d]	50106	1			T54	5		T59	198		T103	48
valid_sources[0x1e]	50299	1			T54	2		T59	179		T103	43
valid_sources[0x1f]	49067	1			T54	7		T56	1		T59	209
valid_sources[0x20]	48766	1			T55	1		T59	231		T103	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45832

1

T54

2

T55

3

T59

232

values[0x0]

all_enables

biggest_size

343076

1

T54

23

T56

6

T59

1584

values[0x1]

all_enables

biggest_size

45991

1

T54

5

T55

1

T56

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2953366	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

480221

1

T54

29

T55

5

T56

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1175335	1			T54	54		T55	21		T56	53
values[0x0]	1082469	1			T54	73		T55	2		T56	48
values[0x1]	1175783	1			T54	62		T55	17		T56	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2266854	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1166733

1

T54

65

T55

17

T56

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54341	1			T55	1		T56	2		T59	212
valid_sources[0x01]	53458	1			T54	14		T55	1		T56	1
valid_sources[0x02]	53786	1			T55	1		T56	3		T59	255
valid_sources[0x03]	53485	1			T56	5		T59	188		T103	33
valid_sources[0x04]	54633	1			T54	4		T55	1		T59	304
valid_sources[0x05]	52338	1			T54	2		T56	6		T59	315
valid_sources[0x06]	53959	1			T56	1		T59	262		T103	34
valid_sources[0x07]	53589	1			T55	1		T56	2		T59	237
valid_sources[0x08]	53882	1			T56	1		T59	185		T103	48
valid_sources[0x09]	52627	1			T54	20		T55	1		T56	1
valid_sources[0x0a]	53681	1			T56	3		T59	259		T103	34
valid_sources[0x0b]	53814	1			T54	3		T56	4		T59	250
valid_sources[0x0c]	52862	1			T59	236		T103	37		T507	1
valid_sources[0x0d]	53186	1			T56	4		T59	265		T103	29
valid_sources[0x0e]	53925	1			T55	1		T56	1		T59	244
valid_sources[0x0f]	53055	1			T56	4		T59	270		T103	40
valid_sources[0x10]	53136	1			T55	1		T56	3		T59	277
valid_sources[0x11]	53823	1			T55	1		T56	1		T59	225
valid_sources[0x12]	54272	1			T55	4		T56	3		T59	255
valid_sources[0x13]	54142	1			T54	7		T59	248		T103	33
valid_sources[0x14]	54383	1			T59	152		T103	45		T405	32
valid_sources[0x15]	53155	1			T55	1		T59	234		T103	40
valid_sources[0x16]	53863	1			T55	2		T56	1		T59	260
valid_sources[0x17]	53643	1			T54	5		T55	3		T59	222
valid_sources[0x18]	54485	1			T56	3		T59	345		T103	38
valid_sources[0x19]	54064	1			T54	1		T59	264		T103	33
valid_sources[0x1a]	53392	1			T54	6		T56	3		T59	281
valid_sources[0x1b]	52300	1			T54	1		T56	5		T59	257
valid_sources[0x1c]	53409	1			T55	4		T56	3		T59	298
valid_sources[0x1d]	53689	1			T54	4		T55	1		T56	3
valid_sources[0x1e]	54267	1			T54	6		T59	180		T103	39
valid_sources[0x1f]	53707	1			T54	5		T55	1		T56	5
valid_sources[0x20]	52577	1			T54	4		T59	196		T103	49

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50491

1

T54

5

T55

2

T56

5

values[0x0]

all_enables

biggest_size

379216

1

T54

24

T55

1

T56

19

values[0x1]

all_enables

biggest_size

50514

1

T55

2

T56

3

T59

247

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2776346	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

438520

1

T54

26

T55

5

T56

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1089719	1			T54	51		T55	25		T56	56
values[0x0]	1035272	1			T54	53		T55	4		T56	47
values[0x1]	1089875	1			T54	65		T55	21		T56	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2148870	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1065996

1

T54

62

T55

16

T56

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52009	1			T55	2		T56	3		T59	197
valid_sources[0x01]	50582	1			T55	1		T56	8		T59	260
valid_sources[0x02]	50773	1			T55	1		T56	3		T59	236
valid_sources[0x03]	50015	1			T54	3		T55	2		T59	197
valid_sources[0x04]	50174	1			T55	1		T56	1		T59	237
valid_sources[0x05]	50745	1			T55	2		T56	1		T59	230
valid_sources[0x06]	50442	1			T54	15		T56	2		T59	308
valid_sources[0x07]	49672	1			T54	2		T55	1		T56	2
valid_sources[0x08]	49543	1			T56	4		T59	167		T103	45
valid_sources[0x09]	49850	1			T55	2		T59	207		T103	32
valid_sources[0x0a]	50132	1			T55	1		T59	198		T103	37
valid_sources[0x0b]	50396	1			T55	2		T56	4		T59	205
valid_sources[0x0c]	51159	1			T55	2		T59	229		T103	28
valid_sources[0x0d]	49636	1			T56	1		T59	236		T103	36
valid_sources[0x0e]	50086	1			T54	3		T56	4		T59	231
valid_sources[0x0f]	49293	1			T59	207		T103	30		T507	2
valid_sources[0x10]	50250	1			T56	9		T59	243		T103	45
valid_sources[0x11]	50403	1			T54	28		T55	2		T59	257
valid_sources[0x12]	50250	1			T59	242		T103	22		T507	1
valid_sources[0x13]	49860	1			T54	17		T55	1		T59	231
valid_sources[0x14]	50613	1			T55	5		T59	197		T103	24
valid_sources[0x15]	50737	1			T55	2		T59	272		T103	30
valid_sources[0x16]	50841	1			T56	10		T59	247		T103	40
valid_sources[0x17]	49510	1			T55	1		T56	14		T59	189
valid_sources[0x18]	50437	1			T54	2		T56	2		T59	339
valid_sources[0x19]	50012	1			T56	5		T59	214		T103	30
valid_sources[0x1a]	50512	1			T56	1		T59	302		T103	33
valid_sources[0x1b]	49064	1			T56	7		T59	303		T103	55
valid_sources[0x1c]	49315	1			T56	1		T59	226		T103	27
valid_sources[0x1d]	50117	1			T56	6		T59	203		T103	34
valid_sources[0x1e]	50507	1			T54	2		T56	1		T59	205
valid_sources[0x1f]	49521	1			T55	2		T56	1		T59	204
valid_sources[0x20]	49399	1			T55	1		T56	2		T59	204

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46044

1

T54

1

T55

3

T56

1

values[0x0]

all_enables

biggest_size

346181

1

T54

22

T55

1

T56

15

values[0x1]

all_enables

biggest_size

46295

1

T54

3

T55

1

T59

208