dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_54

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_55

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_56

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_18

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_19

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_20

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_21

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_22

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_23

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_24

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_25

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_26

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_27

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_28

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.19 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_54
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_55
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_56
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_0
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_1
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_2
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_3
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_4
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_5
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_6
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_7
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_8
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_9
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_10
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_11
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_12
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_13
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_14
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_15
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_16
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_17
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_18
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_19
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_20
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_21
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_22
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_23
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_24
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_25
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_26
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_27
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_28
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_54
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_54
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T18,T35

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_54
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T16,T18,T35
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T16,T18,T35
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_55
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_55
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT35,T190,T20

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_55
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T35,T190,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T35,T190,T20
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_56
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_56
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T22,T23

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_56
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T17,T22,T23
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T17,T22,T23
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_0
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_0
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T401

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_0
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T401
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_1
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_1
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T426

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_1
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T426
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_2
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_2
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT59,T166,T350

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_2
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T59,T166,T350
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_3
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_3
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T524

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_3
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T524
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_4
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_4
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T431

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_4
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T431
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_5
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_5
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T421

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_5
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T421
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T168
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_6
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_6
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T513,T350

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_6
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T513,T350
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_7
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_7
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T427

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_7
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T427
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_8
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_8
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T558

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_8
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T558
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_9
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_9
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T417

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_9
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T417
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_10
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_10
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T415

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_10
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T415
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_11
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_11
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T401

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_11
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T401
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T168
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_12
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_12
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T427

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_12
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T427
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_13
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_13
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T417

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_13
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T417
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_14
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_14
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T500

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_14
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T500
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_15
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_15
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T416

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_15
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T416
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_16
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_16
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T386

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_16
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T386
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_17
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_17
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT59,T103,T166

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_17
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T59,T103,T166
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_18
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_18
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T402

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_18
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T402
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_19
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_19
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T402

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_19
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T402
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_20
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_20
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT405,T166,T404

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_20
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T405,T166,T404
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_21
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_21
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T521,T350

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_21
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T521,T350
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_22
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_22
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T401

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_22
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T401
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_23
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_23
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T523

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_23
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T523
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_24
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_24
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T402

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_24
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T402
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_25
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_25
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T498,T350

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_25
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T498,T350
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_26
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_26
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T416

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_26
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T416
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_27
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_27
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T417

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_27
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T417
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_28
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_28
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT166,T350,T574

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_outsel_regwen_28
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T166,T350,T574
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T166,T350,T167
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%