Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	373794584	43308149	0	0
DepthKnown_A	373794584	373704823	0	0
RvalidKnown_A	373794584	373704823	0	0
WreadyKnown_A	373794584	373704823	0	0
gen_passthru_fifo.paramCheckPass	911	911	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	43308149	0	0
T1	301011	33224	0	0
T2	145559	15031	0	0
T3	74838	6831	0	0
T4	247113	6121	0	0
T16	608791	83652	0	0
T32	221084	69025	0	0
T45	121858	11802	0	0
T91	407722	52262	0	0
T93	392002	38326	0	0
T97	137592	23580	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	373704823	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	373704823	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	373704823	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	911	911	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T32	1	1	0	0
T45	1	1	0	0
T91	1	1	0	0
T93	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	373794584	34563936	0	0
DepthKnown_A	373794584	373704823	0	0
RvalidKnown_A	373794584	373704823	0	0
WreadyKnown_A	373794584	373704823	0	0
gen_passthru_fifo.paramCheckPass	911	911	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	34563936	0	0
T1	301011	25763	0	0
T2	145559	11010	0	0
T3	74838	4605	0	0
T4	247113	4178	0	0
T16	608791	59370	0	0
T32	221084	35172	0	0
T45	121858	8070	0	0
T91	407722	49119	0	0
T93	392002	34753	0	0
T97	137592	15914	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	373704823	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	373704823	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	373704823	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	911	911	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T32	1	1	0	0
T45	1	1	0	0
T91	1	1	0	0
T93	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	373794584	33047771	0	0
DepthKnown_A	373794584	373704823	0	0
RvalidKnown_A	373794584	373704823	0	0
WreadyKnown_A	373794584	373704823	0	0
gen_passthru_fifo.paramCheckPass	911	911	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	33047771	0	0
T1	301011	19068	0	0
T2	145559	11553	0	0
T3	74838	3165	0	0
T4	247113	3342	0	0
T16	608791	37191	0	0
T32	221084	24129	0	0
T45	121858	6528	0	0
T91	407722	43640	0	0
T93	392002	32564	0	0
T97	137592	7498	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	373704823	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	373704823	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	373704823	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	911	911	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T32	1	1	0	0
T45	1	1	0	0
T91	1	1	0	0
T93	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	373794584	27380556	0	0
DepthKnown_A	373794584	373704823	0	0
RvalidKnown_A	373794584	373704823	0	0
WreadyKnown_A	373794584	373704823	0	0
gen_passthru_fifo.paramCheckPass	911	911	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	27380556	0	0
T1	301011	18627	0	0
T2	145559	11264	0	0
T3	74838	3025	0	0
T4	247113	3225	0	0
T16	608791	35858	0	0
T32	221084	15133	0	0
T45	121858	6286	0	0
T91	407722	43463	0	0
T93	392002	32413	0	0
T97	137592	7220	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	373704823	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	373704823	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373794584	373704823	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	911	911	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T32	1	1	0	0
T45	1	1	0	0
T91	1	1	0	0
T93	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461552245	95270	0	0
DepthKnown_A	461552245	461450212	0	0
RvalidKnown_A	461552245	461450212	0	0
WreadyKnown_A	461552245	461450212	0	0
gen_passthru_fifo.paramCheckPass	2801	2801	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	95270	0	0
T1	301011	64	0	0
T2	145559	94	0	0
T3	74838	19	0	0
T4	247113	15	0	0
T16	608791	122	0	0
T32	221084	26	0	0
T45	121858	27	0	0
T91	407722	17	0	0
T93	392002	33	0	0
T97	137592	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2801	2801	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T32	1	1	0	0
T45	1	1	0	0
T91	1	1	0	0
T93	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461552245	97753	0	0
DepthKnown_A	461552245	461450212	0	0
RvalidKnown_A	461552245	461450212	0	0
WreadyKnown_A	461552245	461450212	0	0
gen_passthru_fifo.paramCheckPass	2801	2801	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	97753	0	0
T1	301011	64	0	0
T2	145559	94	0	0
T3	74838	19	0	0
T4	247113	14	0	0
T16	608791	122	0	0
T32	221084	26	0	0
T45	121858	27	0	0
T91	407722	17	0	0
T93	392002	33	0	0
T97	137592	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2801	2801	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T32	1	1	0	0
T45	1	1	0	0
T91	1	1	0	0
T93	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461552245	47245	0	0
DepthKnown_A	461552245	461450212	0	0
RvalidKnown_A	461552245	461450212	0	0
WreadyKnown_A	461552245	461450212	0	0
gen_passthru_fifo.paramCheckPass	2801	2801	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	47245	0	0
T1	301011	59	0	0
T2	145559	93	0	0
T3	74838	18	0	0
T4	247113	14	0	0
T16	608791	104	0	0
T32	221084	24	0	0
T45	121858	25	0	0
T91	407722	16	0	0
T93	392002	32	0	0
T97	137592	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2801	2801	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T32	1	1	0	0
T45	1	1	0	0
T91	1	1	0	0
T93	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461552245	47244	0	0
DepthKnown_A	461552245	461450212	0	0
RvalidKnown_A	461552245	461450212	0	0
WreadyKnown_A	461552245	461450212	0	0
gen_passthru_fifo.paramCheckPass	2801	2801	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	47244	0	0
T1	301011	59	0	0
T2	145559	93	0	0
T3	74838	18	0	0
T4	247113	13	0	0
T16	608791	104	0	0
T32	221084	24	0	0
T45	121858	25	0	0
T91	407722	16	0	0
T93	392002	32	0	0
T97	137592	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2801	2801	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T32	1	1	0	0
T45	1	1	0	0
T91	1	1	0	0
T93	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461552245	48025	0	0
DepthKnown_A	461552245	461450212	0	0
RvalidKnown_A	461552245	461450212	0	0
WreadyKnown_A	461552245	461450212	0	0
gen_passthru_fifo.paramCheckPass	2801	2801	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	48025	0	0
T1	301011	5	0	0
T2	145559	1	0	0
T3	74838	1	0	0
T4	247113	1	0	0
T16	608791	18	0	0
T32	221084	2	0	0
T45	121858	2	0	0
T91	407722	1	0	0
T93	392002	1	0	0
T97	137592	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2801	2801	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T32	1	1	0	0
T45	1	1	0	0
T91	1	1	0	0
T93	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	461552245	50509	0	0
DepthKnown_A	461552245	461450212	0	0
RvalidKnown_A	461552245	461450212	0	0
WreadyKnown_A	461552245	461450212	0	0
gen_passthru_fifo.paramCheckPass	2801	2801	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	50509	0	0
T1	301011	5	0	0
T2	145559	1	0	0
T3	74838	1	0	0
T4	247113	1	0	0
T16	608791	18	0	0
T32	221084	2	0	0
T45	121858	2	0	0
T91	407722	1	0	0
T93	392002	1	0	0
T97	137592	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461552245	461450212	0	0
T1	301011	300866	0	0
T2	145559	145497	0	0
T3	74838	74780	0	0
T4	247113	247000	0	0
T16	608791	608498	0	0
T32	221084	220974	0	0
T45	121858	121752	0	0
T91	407722	407671	0	0
T93	392002	391940	0	0
T97	137592	137537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2801	2801	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T32	1	1	0	0
T45	1	1	0	0
T91	1	1	0	0
T93	1	1	0	0
T97	1	1	0	0