Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.85	89.96		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.85	89.96		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.85	89.96		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.85	89.96		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T194,T5,T200	Yes	T194,T5,T200	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T194,T5,T200	Yes	T194,T5,T200	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	INPUT
tl_i.a_valid	Yes	Yes	T194,T5,T200	Yes	T194,T5,T200	INPUT
tl_o.a_ready	Yes	Yes	T194,T5,T200	Yes	T194,T5,T200	OUTPUT
tl_o.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T194,T5,T200	Yes	T194,T5,T200	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T194,T5,T200	Yes	T194,T5,T200	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T194,T5,T200	Yes	T194,T5,T200	OUTPUT
tl_o.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T57,*T169,*T54	Yes	T57,T169,T54	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T194,*T5,*T200	Yes	T194,T5,T200	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T194,T5,T200	Yes	T194,T5,T200	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T63,T172	Yes	T70,T63,T172	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T70,T71,T640	Yes	T70,T71,T72	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T70,T71,T72	Yes	T70,T71,T640	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T63,T172	Yes	T70,T63,T172	OUTPUT
cio_rx_i	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T194,T5,T200	Yes	T194,T5,T200	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T194,T200,T116	Yes	T194,T200,T116	OUTPUT
intr_rx_watermark_o	Yes	Yes	T194,T200,T116	Yes	T194,T200,T116	OUTPUT
intr_tx_empty_o	Yes	Yes	T194,T200,T116	Yes	T194,T200,T116	OUTPUT
intr_rx_overflow_o	Yes	Yes	T194,T200,T116	Yes	T194,T200,T116	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_break_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_timeout_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	INPUT
tl_i.a_valid	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	INPUT
tl_o.a_ready	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	OUTPUT
tl_o.d_error	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T57,*T169,*T55	Yes	T57,T169,T54	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T55,T59,T103	Yes	T54,T55,T59	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T200,*T6	Yes	T5,T200,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T63,T71	Yes	T70,T63,T71	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T70,T71,T640	Yes	T70,T71,T72	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T70,T71,T72	Yes	T70,T71,T640	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T63,T71	Yes	T70,T63,T71	OUTPUT
cio_rx_i	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T5,T200,T6	Yes	T5,T200,T6	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T200,T201,T202	Yes	T200,T201,T202	OUTPUT
intr_rx_watermark_o	Yes	Yes	T200,T201,T202	Yes	T200,T201,T202	OUTPUT
intr_tx_empty_o	Yes	Yes	T200,T201,T202	Yes	T200,T201,T202	OUTPUT
intr_rx_overflow_o	Yes	Yes	T200,T201,T202	Yes	T200,T201,T202	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_break_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_timeout_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T194,T116,T196	Yes	T194,T116,T196	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T194,T116,T196	Yes	T194,T116,T196	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	INPUT
tl_i.a_valid	Yes	Yes	T194,T63,T116	Yes	T194,T63,T116	INPUT
tl_o.a_ready	Yes	Yes	T194,T63,T116	Yes	T194,T63,T116	OUTPUT
tl_o.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T194,T116,T196	Yes	T194,T116,T196	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T194,T116,T196	Yes	T194,T63,T116	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T194,T116,T196	Yes	T194,T63,T116	OUTPUT
tl_o.d_sink	Yes	Yes	T54,T55,T59	Yes	T54,T55,T59	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T57,*T169,*T54	Yes	T57,T169,T54	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T194,*T116,*T196	Yes	T194,T116,T196	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T194,T63,T116	Yes	T194,T63,T116	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T63,T172	Yes	T70,T63,T172	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T63,T172	Yes	T70,T63,T172	OUTPUT
cio_rx_i	Yes	Yes	T194,T33,T116	Yes	T194,T33,T116	INPUT
cio_tx_o	Yes	Yes	T194,T116,T196	Yes	T194,T116,T196	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T194,T116,T196	Yes	T194,T116,T196	OUTPUT
intr_rx_watermark_o	Yes	Yes	T194,T116,T196	Yes	T194,T116,T196	OUTPUT
intr_tx_empty_o	Yes	Yes	T194,T116,T196	Yes	T194,T116,T196	OUTPUT
intr_rx_overflow_o	Yes	Yes	T194,T116,T196	Yes	T194,T116,T196	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_break_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_timeout_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T170,T291,T303	Yes	T170,T291,T303	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T170,T291,T303	Yes	T170,T291,T303	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	INPUT
tl_i.a_valid	Yes	Yes	T63,T170,T291	Yes	T63,T170,T291	INPUT
tl_o.a_ready	Yes	Yes	T63,T170,T291	Yes	T63,T170,T291	OUTPUT
tl_o.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T170,T291,T303	Yes	T170,T291,T303	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T170,T291,T303	Yes	T63,T170,T291	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T170,T291,T303	Yes	T63,T170,T291	OUTPUT
tl_o.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T57,*T169,*T54	Yes	T57,T169,T54	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T170,*T291,*T303	Yes	T170,T291,T303	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T63,T170,T291	Yes	T63,T170,T291	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T63,T639	Yes	T70,T63,T639	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T70,T71,T72	Yes	T71,T72,T74	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T71,T72,T74	Yes	T70,T71,T72	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T63,T639	Yes	T70,T63,T639	OUTPUT
cio_rx_i	Yes	Yes	T170,T303,T308	Yes	T170,T303,T308	INPUT
cio_tx_o	Yes	Yes	T170,T303,T57	Yes	T170,T303,T57	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T170,T291,T303	Yes	T170,T291,T303	OUTPUT
intr_rx_watermark_o	Yes	Yes	T170,T291,T303	Yes	T170,T291,T303	OUTPUT
intr_tx_empty_o	Yes	Yes	T170,T291,T303	Yes	T170,T291,T303	OUTPUT
intr_rx_overflow_o	Yes	Yes	T170,T291,T303	Yes	T170,T291,T303	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_break_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_timeout_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T32,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T292	Yes	T14,T15,T292	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T15,T292	Yes	T14,T15,T292	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T32,*T44,*T57	Yes	T32,T44,T57	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T44,T57,T58	Yes	T44,T57,T58	INPUT
tl_i.a_valid	Yes	Yes	T63,T14,T15	Yes	T63,T14,T15	INPUT
tl_o.a_ready	Yes	Yes	T63,T14,T15	Yes	T63,T14,T15	OUTPUT
tl_o.d_error	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T292	Yes	T14,T15,T292	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T14,T15,T292	Yes	T63,T14,T15	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T15,T292	Yes	T63,T14,T15	OUTPUT
tl_o.d_sink	Yes	Yes	T54,T55,T56	Yes	T54,T55,T59	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T57,*T169,*T54	Yes	T57,T169,T54	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T15,*T292	Yes	T14,T15,T292	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T63,T14,T15	Yes	T63,T14,T15	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T70,T63,T118	Yes	T70,T63,T118	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T70,T71,T72	Yes	T71,T72,T74	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T71,T72,T74	Yes	T70,T71,T72	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T70,T63,T118	Yes	T70,T63,T118	OUTPUT
cio_rx_i	Yes	Yes	T14,T15,T292	Yes	T14,T15,T292	INPUT
cio_tx_o	Yes	Yes	T14,T15,T292	Yes	T14,T15,T292	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T14,T15,T292	Yes	T14,T15,T292	OUTPUT
intr_rx_watermark_o	Yes	Yes	T14,T15,T292	Yes	T14,T15,T292	OUTPUT
intr_tx_empty_o	Yes	Yes	T14,T15,T292	Yes	T14,T15,T292	OUTPUT
intr_rx_overflow_o	Yes	Yes	T14,T15,T292	Yes	T14,T15,T292	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_break_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_timeout_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T291,T299,T307	Yes	T291,T299,T307	OUTPUT

*Tests covering at least one bit in the range